By Debra Vogler, Senior Technical Editor, Solid State Technology
Peter Jenkins, VP of marketing for ASML, described lithography options and challenges at the 32nm half-pitch for ConFab attendees. Among the challenges: there is no clear consensus on the part of IC manufacturers with respect to the kind of lithography needed at 32nm, although EUV is preferred for 22nm half-pitch. In a poll of 14 end users, Jenkins reported that memory manufacturers preferred EUV at the 32nm node, but 193nm immersion with single or double exposure was preferred by logic manufacturers.
There are actually three lithography options at 32nm, which is supposed to be introduced in 2009. The first two are 193nm immersion lithography with either a k1=0.22, or a k1=0.26. The second is EUV lithography (13.5nm) with a k1=0.59. A k1=0.22 option would require pitch relaxation or double patterning, while a k1=0.26 would need new fluids and materials. A k1=0.59 option means EUV with its infrastructure challenges.
According to Jenkins, the timing and performance of new glass and fluid will be critical for making high-index immersion lithography a reality, particularly when k1 must be lower, but he noted that some combinations of NA and refractive indices would only allow for an extension less than a full technology node. “No new lithography technology has been successfully introduced for just one node,” he noted.
Double patterning (k1<0.25) would enable the extension of proven lithography by approximately one technology node, said Jenkins, but it has the highest cost impact. EUV, when executed correctly, is expected to be the lowest cost and most extensible to other nodes, but infrastructure development is the remaining challenge. With three alternatives -- all with benefits and drawbacks -- it is clear the industry has some work to do. -- D.V.