Suss, IBM readying C4NP toolset

May 30, 2006 – Suss MicroTec said it has completed initial reliability testing with IBM for 300mm lead-free C4NP solder-bumped wafers, and is building a high-volume manufacturing toolset for IBM.

The tests involved bumping 300mm wafers with SnCu and SnAg solders, using a 200µm pitch with 1.3 million bumps/wafer test vehicle. the 14.7 sq. mm chips were joined to organic buildup chip carriers, and subjected to a variety of tests, including: JEDEC moisture level 3 preconditioning, shock and vibration, deep thermal cycling (-55 to + 125°C), HAST and THB moisture stressing, high temperature storage, electromigration, wettability, construction analysis, and Alpha emissions

IBM ordered the C4NP (“controlled collapse chip connection new process”) high-volume bumping line in September 2005, after a year of development work with Suss. A prototype fully automatic line, designed to accommodate 300 wafer starts/day, was built at Suss’ facilities in Waterbury Center, VT, and installed at IBM’s facilities in East Fishkill, NY.

C4NP offers an alternative method for applying flip-chip solder to wafers compared to traditional photo stencil/screening, electroplating, and evaporative techniques, the companies claimed, when they announced their partnership in September 2004. In the C4NP process, reusable glass molds are filled with molten solder and then applied to the wafers. After a reflow step, the glass mold is removed from the wafer, leaving solder bumps.

The C4NP process easily accommodates binary, ternary, and quaternary alloys, and minimizes the cost of consumables because only solder balls are created and transferred to the wafer without waste, the companies said. The C4NP also supports solder bumping of 200mm and 300mm wafers with similar efficiency.


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