TSMC ramping 65nm process

May 18, 2006 – Taiwan Semiconductor Manufacturing Co. (TSMC) says it has fully qualified its 65nm low-power process technology, with several products already ramped and delivering production volumes.

The new 65nm process is the company’s third-generation process, offering 9-layer metal process with core voltages of 1.0 or 1.2V, and I/O voltages of 1.8, 2.5, or 3.3V. It supports standard cell gate density twice that of TSMC’s 90nm Nexsys process, and features “very competitive” 6T SRAM and 1T embedded DRAM memory cell sizes, the company claims. The process is supported by TSMC’s design support ecosystem (announced days ago) and Reference Flow 6.0, as well as a variety of in-house and third-party libraries and IP.

“At 65nm geometries, we can produce highly integrated, very small and low power devices for every conceivable market,” stated Rick Tsai, TSMC president and CEO.


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