June 15, 2006 – European research consortium IMEC says it has achieved “several breakthroughs” on Ni-based fully silicided (FUSI) gates, achieving “excellent” low-power and high-performance specifications that meet ITRS requirements for use in 45nm-process manufacturing. Results of IMEC’s work with FUSI were presented at the 2006 VLSI Symposium.

To eliminate the gate depletion effect and enhance transistor performance, metal gates are being introduced as a replacement of conventional poly-Si gates. Ni-based FUSI has received a growing attention for sub-45nm CMOS applications since it eliminates poly depletion, it is compatible with high-k dielectrics, it’s a known material in industry and can be integrated in a conventional CMOS flow.

FUSI gates on HfSiON achieved unloaded delay of 17ps at an I of 20pA/µm, and VDD of 1.1V. Using metal gates with FUSI further reduced gate length to 7nm for nMOS and 14nm for pMOS over poly-Si/SiON. IMEC also said that metal gate on HfSiON devices can outperform conventional Poly-Si/SiON 65nm devices by up to 25%.

In a standard flow, poly-Si and spacer heights are not well controlled before FUSI due to non-uniformity in the CMP process and the need for over-etch at oxide etch-back. Incorporating a novel sacrificial SiGe cap at gate level improved the process window, manufacturability and reliability, IMEC claimed. The SiGe cap is deposited on the poly-Si film to absorb the process variability resulting in an opening of the process window from ~5°C to
~20°C, meeting manufacturing requirements.

In addition, IMEC said it had achieved a Vt control with o~19mV (nMOS) and o~21mV (pMOS), including wafer to wafer variation. For a 10-yr lifetime, operating voltages of up to 1V were extrapolated for nMOS and up to 1.2V for pMOS devices, with controlled NiSi and Ni31Si12 or Ni2Si FUSI gates, making it a reliable process.

Also, to help modulate the work function covering low-Vt to high-Vt in Ni-FUSI devices, IMEC says it has developed a practical method to incorporate Ytterbium (Yb) into the gate — by pre-doping into poly-Si through ion implementation — which enables modulation of the Vt for nFETs. The Vt of pFETs is reduced using a Pt alloy into Ni2Si FUSI, and by applying a strained Si0.8Ge0.2 channel. Vt’s down to 0.25V for nFET (NiSi:Yb) and pFET (Ni2Si:Pt + SiGe channel) were achieved on SiON without degradation of the dielectric integrity and long channel mobility.