Intel touts CMOS tri-gate integration

by Debra Vogler, Senior Technical Editor, and James Montgomery, News Editor, Solid State Technology

June 12, 12006 — Intel Corp. is ready to present results of its work with CMOS tri-gate transistors, touting its successful integration of high-k gate dielectrics, metal gate electrodes, and strained silicon to offer considerably lower leakage and consume much less power than today’s planar transistors. The devices could become the basic building blocks for future microprocessors beyond the 45nm node, the company explained, in a pre-briefing before displaying the full results of its work at the VLSI Symposium in Hawaii on June 13.

The company hasn’t made a decision yet as to whether this technology will go into production at the 32nm or 22nm nodes — it is also working on other technology options for those nodes. If the company adopts this particular tri-gate technology, it would be utilized across all microprocessor product lines, according to Mike Mayberry, director of components research and VP of Intel’s technology and manufacturing group. The way the device would be optimized (speed, power, or in-between) would depend on whether it was to be used for a desktop, server, or mobile application.

Mayberry noted that the company is nowhere near having a test chip with a billion transistors (with this architecture), but said they have made small arrays of these devices and the next steps will be to make increasingly larger arrays in order to understand the manufacturing “gotchas.” If the company decides to use this transistor architecture for high-volume manufacturing, it would take approximately a couple of years development time — i.e., until somewhere around the end of the decade, plus or minus a year.

Intel’s tri-gate structure, first announced in September 2002, surrounds the channel on three of four sides. Using high-k and metal gates improves both on and off current. High-k enables a more efficient coupling of the field into the channel — i.e., making it easier to switch the current on or off, so the device can run both faster and cooler at the same time, noted Mayberry. Adding strain improves the mobility, and also results in faster, cooler operation.

Overall, less power is wasted by the integration of these three technologies. Compared with today’s 65nm transistors, this integrated tri-gate transistor can offer speed increases up to 45% (when optimized for speed) than what’s available at the 65nm node, or if the user wants to optimize for power, the standby current can be reduced 50x, according to Mayberry. Still another mid-way choice is a 35% reduction in total power at constant speed when optimizing both active and off current. “You can pick a different operating point depending on the choices of whether you want a battery-powered device, in which case you would probably pick a very low-standby current, or whether you want a little more speed,” noted Mayberry.

The company did not disclose details about what it used for a high-k gate dielectric and metal gate electrode. “The company has literally done thousands of experiments to find the right combination of materials,” said Mayberry, although he indicated that the high-k material is Hafnium-based. — D.V., J.M.


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