by Ed Korczynski, Senior Technical Editor, Solid State Technology
The 9th annual International Interconnect Technology Conference (IITC 2006) again brought together more than 700 of the world’s leading semiconductor manufacturers, alliances, equipment and materials suppliers, and advanced research centers (e.g. IMEC, SELETE, SEMATECH, etc.) in Burlingame, CA, for three days of comparing notes and competing for bragging-rights. Attendees saw detailed information on likely 45nm dual-damascene Cu/porous-low-k integration. The Crolles2Alliance, Hitachi, Infineon, and Matsushita each showed that dielectric “air-gap” large structured pores may be used instead of random nano-pores to provide comparable electrical and mechanical results, and may be a less expensive manufacturing alternative.
Technology experts from North America, Europe, and Asia presented over 40 oral presentations and 28 posters covering topics including materials, integration, reliability, and modeling. “Feedback has been very positive, particularly about the quality of the papers,” noted Chris Case, CTO of BOC Edwards and general chair of the conference. “The IITC community appreciates both high quality technical content, and great peer networking opportunities.” Lunches, breaks, and the 11 supplier events in the evenings allowed time to rub-shoulders with true world-leaders.
IITC participants also provided a glimpse into what may come next for chipmaking technologies. Applied Materials, Crolles2Alliance, IBM/Stanford, IMEC/Philips/ASM, Sony, and Toshiba all showed visions of 32nm node dual-damascene Cu/low-k interconnects. Plus, IMEC looked at Cu contacts for the 22nm node, and Fujitsu showed substantial progress in developing manufacturing processes to grow carbon nanotubes (CNT) as on-chip conductors (see figure).
Researchers from IMEC, along with Neocera and Intel (and ASM Japan who provided the low-k material), examined various 65nm dielectric integration schemes with a particular focus upon plasma etch processes for dual-damascene process flows. Using surface acoustic waves (SAW) frequency shifts, researchers could detect dielectric damage due to different etch chemistries. Depending upon the particular etch-chemistry and whether the etch process may be tuned to induce sidewall polymers, the as-deposited low-k material (k~2.5) varied from 2.3 to well over 3.5 in k value. Absorption of -OH radicals is a major concern, since it may be irreversible and can result in a “lossy dielectric.”
The Crolles2Alliance showed their best results from CMOS 45nm SRAM test structures. They use ~2.5 k PLK (with ~0.8nm average pore diameter) for both via and line levels, along with a thin metal barrier. While ~6% of the line cross-section is needed for the 8-10nm thick PVD barrier at 180nm, ~20% of the cross-section would be taken up by the same barrier by 45nm; consequently, 5-6nm thick ALD will be used. With an overall goal of doubling the interconnect density compared with the 65nm node, more hierarchy is imposed — lower levels with the tightest 130-140nm pitches, middle levels with 280nm pitch, and top levels with “fat” 0.8 µm wires.
Usui-san from Toshiba’s Center for Semiconductor R&D discussed 32nm node interconnect formation, including a self-forming manganese silicon oxide (MnSixOy) barrier layer. Starting with dual-damascene trenches and vias, they deposit a 60nm thick alloy of Cu and Mn (40%), ECP fill with Cu, anneal at 250°C, then standard Cu CMP. The anneal step results in the formation of a ~2nm thick MnSixOy barrier layer at the interface between the low-k dielectrics and Cu. An important advantage of this process flow is that no barrier forms at via bottoms, reducing resistance by ~70% (shown on via chain tests).
Matsushita presented on “Air Gap Exclusion” using an additional lithography step, then SiO2 deposition to form pinch-off air-gaps, SiO2 CMP, and finally blanket FSG deposition. By excluding large gaps they avoid degradation of planarity, while excluding small gaps prevents interlayer via shorts. The final structure demonstrated keff ~2.4 within the narrowest lines of local-interconnects. Models show that this should be extendible to the 32nm node.
Researchers from Georgia Tech presented an invited paper on the theoretical limits of on-chip interconnects using carbon nanotubes (CNT) as conductors. For global interconnects, large multiwall CNTs offer the best conductivity, while bundles of single-wall CNTs provide the lowest delay for local interconnects. However, for <1µm lengths, Cu offers conductivities higher than either single-wall or multiwall CNTs.
Shintaro Sato from Fujitsu presented data on CNTs grown inside vias using catalyst particles. Bundles of multiwall CNTs were grown on Co particles by thermal CVD using C2H5 at milliPascal pressures (see Figure). The current best results of ~10 CNTs (assuming ~7nm diameter) grown per 40nm diameter via result in only ~30% filling of the via volume. Thus, there is plenty of room to enhance the growth probability and to nearly fill the vias, which theoretically would provide lower resistance than tungsten.
Spectral photo-response (SPR) of interconnects is a newly discovered metrology technique that can characterize chemical composition, strain, defectivity, and air-gaps in interconnects down to 22nm spacing (theoretically). Non-destructive and highly sensitive, the technique compares the leakage current under illumination — using a standard meander-comb test structure — to the dark leakage current. — E.K.