TI readying 45nm process, mulling metal gate options

June 12, 2006 – Texas Instruments is prepping a 45nm chipmaking process, built with immersion lithography and an ultralow-k dielectric, that it says can double the number of chips/wafer, reduce power consumption by 40%, and boost performance by 30%. The company also laid out options for future processes that can help improve power consumption without requiring a shift to incorporate high-k materials.

The new 45nm process were built using 193nm immersion lithography techniques and an ultralow-k dielectric (k=2.5), which reduces interconnect capacitance by 10%, as well as the company’s first use of silicon germanium in its strain techniques. The device includes TI’s SmartReflex power and performance technologies, and supports its DRP architecture to integrate digital RF functionality in single-chip wireless solutions. SRAM memory cells developed with the technology occupy only 0.24 sq. microns of space, nearly 30% smaller than other 45nm memory cells, the company said.

Also of note, TI said it is considering techniques such as full-silicidation-of-polysilicon (FuSI), or a combination of metal plus a silicide, to utilize a dual work function metal gate “at some point” in its 45nm technology roadmap. Doing so will achieve power consumption control without the need to also move to new and complex high-k materials, the company said.

The company estimates that incorporating the 45nm process into SoCs will deliver up to a 30% performance improvement in device speed, and the power reduction could give cell phones an extra 30% stand-by time.

TI plans to offer several flavors of 45nm recipes, including a low-power offering for portable products, a midrange process for DSPs and an ASIC library for communications infrastructure products, and a high-performance version for MPU-class performance. The low-power ASIC design library will be available by the end of this year, with samples of the SoC product delivered in 2007, and initial production in mid-2008.


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