Auto-fix for hot-spots in nanometer node designs

by Ed Korczynski, senior technical editor

DFM start-up Takumi Technologies, building on its mask-data preparation work for NEC and other customers, is now promoting its ability to automatically detect, classify, and repair yield-limiting design “hot spots” — areas of a design layout which, due to process or geometric conditions, fall outside of process windows, resulting in potential catastrophic or parametric failure.

Two new software tools work in coordination to optimize designs for manufacturability. Takumi’s Inspect software takes in the GDSII layout information after design-rule check (DRC) and then detects and rates hot spots against multiple yield-loss mechanisms. Defects are rated in terms of failure potential in parts-per-billion (ppb), allowing for a realistic estimation of manufacturing yield prior to tapeout. Yield loss mechanisms are evaluated concurrently, including those related to RET/OPC, lithography, random defects, systemic defects, and manufacturing tolerances, eliminating iteration time and minimizing the risk of missing interdependent phenomena. All ratings are performed using foundry-specific defect data.

Takumi’s Enhance software operates on GDSII layout data to detect, rate, and automatically repair hot spots based on critical area, single-contact hole or via, printability and edge-placement errors due to misalignment margins, and contrast issues. Enhance also uses inputs from third-party pre- or post-OPC verification tools to drive a 2D layout optimization, which can reduce the failure rate of a real chip from 96.3 ppb to 79.3 ppb. Users also can develop their own criticality rating functions.

Rules for fixes are fully programmable by the end-user, such as doubled contacts and vias on an “as needed” or a “where possible” basis. On average, each standard-cell in a leading 65-nm node library takes ~30 sec of Enhance software runtime to perform hot-spot correction — a large SoC with 500 standard cells can still be run overnight on a single Opteron 64-bit microprocessor with 32Gbit DRAM.

Working with Toshiba as an early customer, Takumi was given the tough challenge of finding ways to reduce mask costs by 20%. Analysis showed that tape-out labor was one of the greatest variable costs, adding up to ~$400k/month costs just for salary. S. Inoue, group manager of lithography process development group of Toshiba Semiconductor Co.’s Process and Manufacturing Engineering Center, remarked that despite complexity and large data files associated with sub-65nm SoC technology, “we were able to reduce the number of hot spots from over 47,000 to just 40 in 12 hours.”

Takumi says that third-party design solutions like theirs are gaining favor as permanent augmentations to the design-flows of major IDMs. As proof, they site data that IDMs are shifting more of their EDA budget to internal groups, but aren’t hiring more people. “We were working with 45nm data in 2004,” commented Tom Wong, Takumi Technologies’ VP of marketing. “We asked the customer when they would go into production — and they said 2008.” — E.K.


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