Chartered, Singapore university join for 65nm packaging

July 11, 2006 – Chartered Semiconductor Manufacturing and Singapore’s Institute of Microelectronics, part of Singapore’s Agency for Science, Technology and Research (A*STAR), have agreed to collaboration on research to optimize a range of fine-pitch packaging technologies for copper metallization and low-k dielectric silicon processes at 65nm and below.

The research, based on processed developed by Chartered and partners IBM, Infineon, and Samsung Electronics Co., will utilize a large die, copper/low-k test chip structure with a fine bump pitch, investigating the package-level reliability and optimize performance against various fine-pitch packaging technologies such as high-lead solder bump, copper posts, and polymer encapsulation. The teams also plan to develop modeling tools to help capture the correlation between the fine-pitch packaging technologies and test structure stress levels, integrity, and performance. Using those results, researchers hope to evaluate and characterize the impact of under-bump metallurgy on low-k integrity, and the compatibility of underfill materials with low-k structures.

Increasing demand for high-performance system-on-chip product is necessitating use of fine-pitch packages with bump chip pitches below 180µm. However, there is no fine-pitch packaging solution currently available due to implementation challenges and complex interactions between the silicon and packaging technology, Chartered explained.

“With the transition to 65nm, companies are realizing that having a successful backend packaging strategy is a key to realizing volume ramp quickly and meeting time-to-market goals,” stated Liang-Choo Hsia, SVP of technology development at Chartered.

“The research collaboration integrates IME’s proven expertise in backend packaging know-how with Chartered’s success in advanced copper metallization and low-k dielectric process manufacturing,” added Professor Dim-Lee Kwong, Executive Director of IME. “We are excited with the opportunity to work together to resolve one of the industry’s most challenging back-end integration challenges and provide our mutual customers with a reliable path from manufacturing to final chip packaging.”


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