by Ed Korczynski, Senior Technical Editor
Design-rule check (DRC) used to involve simple “go/no-go” checks, but simple compliance is no longer sufficient to account for the variety and complexity of nanometer-era manufacturing processes. To ensure high yield in nanometer-era chips, designers need statistically valid yield analysis based on physically verified models.
Addressing this need, Mentor Graphics has released a new DRC tool, “Calibre nmDRC,” as part of its new fifth-generation Calibrenm platform. Promising order-of-magnitude speed improvement for the same price, the tool integrates elements such as critical-area-analysis (CAA) and critical feature identification, to provide real yield analysis as part of DRC. The product is currently in beta-tests with 30-40 customers, and should be officially released in 3Q06.
Calibrenm DRC determines the location of the most significant yield improvement opportunities, providing graded yield metrics by issue, cell, window, etc. The new software assesses the weighted greyscale of features that fail to meet recommended rules, and compares them to CAA particle sensitivities, such that the designer can evaluate both in the same deck and perform trade-off analyses.
The new software has been re-architected to allow hyperscaling to use shared memory processor systems as well as distributed rack systems in the most efficient manner possible. Designers can thus get the most out of current investments in design hardware (such as existing Linux clusters), and see runtime improvements more than double. Still, the new code drops into the designers existing CAD environment without disruption.
Dynamic results visualization and incremental verification means that cells/blocks and other fundamental design subsets can be handled in parallel, so that debugging can start for some cells while others are still being checked. Combined with faster checking due to the hyperscaled software engine, incremental verification allows dramatically faster iteration on a timescale of hours instead of days.
The underlying Calibrenm Platform uniquely reads all open data formats, including GDSII, OpenAccess, Milkyway, LEF/DEF, and OASIS. Integrated into third-party tools, the database interface automates layer mapping, back-annotates DFM optimizations into the design database, and does not require disk-space to save the GDSII data for every iteration. Also, changing from Standard Verification Rule Format (SVRF) to the higher-level Tcl Verification Format (TVF) for the coding language simplifies rule scripting and maintenance — the code to describe a recommended rule for prioritizing metal line widths is reduced from 509 lines of SVRF to just 64 lines of TVF. — E.K.