Samsung readies 65nm low-power process

July 25, 2006 – Samsung Electronics Co. Ltd. said it has qualified its 65nm low-power process technology, to expand its contract foundry offerings from its S1 300mm logic fab line in Giheung, Korea.

The process offering includes a range of low-leakage to high-performance transistors for low-power applications, with up to nine levels of Cu interconnect. Standard process offerings include SRAM bit cells, optimized for performance or ultralow leakage, e-fuse circuits, and mixed signal device components. The process is also compatible with the common platform technology developed by Samsung partners IBM and Chartered.

“Dynamics in the semiconductor market are moving more companies to rely on high-end contract manufacturing,” stated Ana Molnar Hunter, VP of technology for Samsung Semiconductor’s foundry business. “Our production ready advanced process technology offers our foundry customers the ability to integrate more features while maintaining very low power consumption and a fast ramp into high volume production.”

Last week Samsung said it had ramped to volume production of its 8Gbit NAND flash memory based on multilevel cell (MLC) architecture and 60nm process technologies, and by 3Q06 plans to release an 8GB memory product by stacking two 4GB packages, each with a vertical stack of four 8Gbit dies. The 60nm-based 8Gbit NAND flash will be used in Samsung’s high-density MLC NAND, called “moviNAND,” to produce a 2GB-level NAND device combining NAND flash memory and a NAND controller, to be embedded in mobile handsets.

In June Samsung said it has developed a 2GB version of its OneNAND flash memory device also using 60nm process technology, which it says offers a 25% improvement in manufacturing productivity vs. the previous 70nm design process.


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