Soitec serving up strained SOI wafers

July 12, 2006 – Soitec, Bernin, France, says it is now shipping strained silicon-on-insulator (sSOI) wafers for sub-65nm processing targeting partially and fully depleted device architectures, having transferred its 300mm sSOI platform from development into the first phase of production. The company says the new sSOI wafers offer high mobility advantages of strained silicon, with speed and power dissipation benefits of SOI.

“We will ramp our initial production to meet the needs of early adopters followed by ramps to higher volumes as the mainstream market increasingly turns to this innovative substrate technology,” stated Andre-Jacques Auberton-Herve, company president and CEO.


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