July 26, 2006 – Semiconductor Research Corp., a university-research consortium for semiconductor technologies, the U. of Michigan, and the National Science Foundation (NSF) have announced a joint three-year project to develop defect-tolerant designs for chips “that refuse to fail.”

The trio’s work will focus on analysis of hard silicon failures and their impact on nontrivial designs such as microprocessors and their switch components. The goal is “not to build flawless chips, but architectures that can survive defects,” according to Todd Austin, associate professor of electrical engineering at University of Michigan and a former Intel design engineer. Ultimately the finished product will be chips “that can diagnose when components wear out and heal themselves on the fly,” stated Sankar Basu, program director at NSF.

Current industry efforts to make chips more reliable through redundancy and other traditional means have run into challenges involving higher costs and speed limitations. In comparison, this collaborative research hopes to create defect-tolerant designs incorporating components that take longer to fail, thus increasing product lifetimes. “This issue of ensuring reliability is critical to the future of high-performance computing for even the most aggressive of applications,” noted Basu.

“The ramifications of increasing the reliability of the microprocessor in computing applications like planes, trains and automobiles is something we get very excited about,” added William Joyner, IBM assignee to the SRC, and director computer-aided design and test for the organization’s Global Research Collaboration.