Albany, IMEC parade first EUV tools

August 29, 2006 – European research consortium IMEC and the College of Nanoscale Science and Engineering (CSNE) of the U. at Albany say they have received the first extreme-ultraviolet (EUV) lithography full-field alpha tools from Dutch equipment developer ASML, apparently within days of each other. EUV is considered the most likely candidate for the 32nm half-pitch node.

Both groups will use the EUV tools for R&D to research next-generation lithography. ASML said it shipped the tools after achieving certain lithography performance targets including full-field scanning imaging and overlay. Earlier this year at the SPIE Microlithography conference, the company presented proof-of-concept 35nm resist images obtained over a full slit of 26mm, made on one of these systems.

Although these particular tools are purely for R&D, preproduction EUV tools could be shipped as early as 2009, depending on “customer commitment,” stated Martin van den Brink, EVP, marketing and technology, ASML.

Luc Van den hove, VP of silicon process and device technology at IMEC, noted that IMEC is now running programs in parallel for advanced lithography, double-patterning both ArF immersion and EUV lithography. The EUV program focuses on optical path stability and monitoring; reticle handling (including cleaning) in a wafer fab and defect printability; assessment of line-edge roughness and its relation to shot noise; resist assessment and process optimization; critical layer patterning; and printable defects of EUV masks.

Albany NanoTech said its EUV tool, costing an estimated $65 million, will support R&D programs of its $600 million International Venture for Nanolithography (“INVENT”), a consortium formed in July 2005 and led by IBM, AMD, Infineon, and Micron to develop immersion and extreme-ultraviolet lithography applications.

In early 2005, ASML established a $400 million R&D center at the CNSE’s Albany NanoTech complex, dubbed the International Multiphase Partnership for Lithography Science and Engineering (“IMPLSE”) — the company’s only 300mm wafer R&D facility outside its Netherlands headquarters — to develop nanoscale lithography technologies for future generations of nanochips.

At a recent IEEE Workshop, progress was reported in picking up where optical lithography “ends,” with steady progress on tools, mask handling, and defects. Source remains the largest challenge, with possible solutions including using more photons (slower resist), though that places more demands on EUV source output. Double-exposure techniques likely will be utilized — added costs are a sticking point, but likely would be no less painful than pricetags for super-high NA tools.


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