By W. Luo, D. Thon, Cadence Design Systems

Executive Overview

With the move to more advanced semiconductor manufacturing technologies, semiconductor companies are finding that modifications to physical design data meant to improve yield can seriously impact integrated circuit (IC) performance and functionality.

As a result, IC design houses are focusing growing attention on manufacturing effects at the earliest possible stages of IC design. Increasingly, design engineers are looking to more accurately predict on-chip performance variation caused by downstream chemical mechanical polishing (CMP) and lithography steps.

Yet, practical deployment of manufacturing-aware IC design flows has eluded mainstream IC development because of the inherent difficulties in balancing yield-enhancing manufacturing requirements with performance-optimizing design requirements.

In the future, semiconductor companies looking to maximize yield will need to deploy more effective methods to account for manufacturing effects early in IC development.