Matsushita, Renesas now testing 45nm SoCs

August 3, 2006 – Matsushita Electric Industrial Co. Ltd. and Renesas Technology Corp. say they have entered full integration testing of 45nm system-on-chip (SoC) manufacturing technology. The 45nm process will be used by both companies in manufacturing SoCs for mobile products and networked consumer electronics products.

The process incorporates ArF immersion lithography, with NA?1.0. Other technologies, including introduced-strain high-mobility transistors and extreme low-k (k=2.4) multilayer wiring modules, also will be introduced into the process, which is scheduled to be completed in June 2007 and ramping to volume production in fiscal 2008.

The companies started working on the joint 45nm process in Oct. 2005, after initiating mass-production of 65nm system chips at Matsushita’s plant in Uozu, Toyama Prefecture, in the fall of that year. The 45nm SoC testing phase represents the fifth stage of collaboration, and follows seven years of joint process development, which have included a 130nm DRAM merged process (2001), 90nm SoC (2002), and a 90nm DRAM merged process (2004).

Renesas was originally part of a group of Japanese companies mulling a joint 300mm/65nm advanced chipmaking operation, but a planning group formed by Hitachi, Toshiba, and Renesas to assess the feasibility of the project was broken up in June after concluding that such a project is currently not feasible.

Meanwhile, Toshiba, Fujitsu Ltd., NEC Electronics Corp., and Renesas Technology Corp. have stated they would work together to develop standardization of 45nm- and below process technologies for large-scale integration (LSI) chips, emphasizing certain aspects such as effective re-use of IP and libraries. Following technical studies, these standardization efforts are expected to be defined by year’s end, according to local reports.


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