by Jeff Demmin, Contributing Editor, WaferNews
Recent advances in packaging technology from NEC, Freescale, and Micron indicate that integrated device manufacturers (IDMs) ¿ not packaging specialists ¿ are making some of the most important strides in the field these days. These new technologies, leveraging the companies’ wafer-processing expertise, involve significant changes to chip packaging technology, rather than just an incremental improvement in package design, such as package thickness or the number of chips in a stack.
Freescale, for example, introduced “redistributed chip packaging” (RCP), an update to the “chips-first” multi-chip packaging approach pursued by several companies early in the multi-chip module era (1980s and 1990s). Freescale’s RCP approach involves mounting a variety of singulated chips on a panel that can be sent through conventional wafer processing steps. After the chips are mounted, deposition, photolithography, and etching are used to pattern interconnect and dielectric layers on top of the chips. This interconnect replaces wire bonding or flip chip as the means for making electrical connections to the chips. To demonstrate RCP, Freescale rolled out a GSM module incorporating RF, baseband, power amplifier, and power management chips. High-volume availability of Freescale’s RCP technology is expected in 2008.
This technology is especially useful when combining different types of chips, and it can provide a significant advantage for companies that produce or have access to a variety of chips in die format. A company that has to procure packaged devices from multiple suppliers would have technical and logistical difficulties producing such a highly miniaturized module. Large IDMs such as Freescale that produce many kinds of chips are thus able to gain greater benefit from advanced packaging technology than smaller competitors. Large IDMs also have an advantage over packaging sub-contractors because they control access to the die.
Micron’s new packaging technology announcement was also more of a preview of what it is working on, rather than a new technology available in production now. The technology, dubbed “Osmium” (in reference to the most dense element on the Periodic Table), involves several advances in wafer-level processing: through-wafer interconnects consisting of vias drilled through bond pads to allow connections between wafers; new redistribution layer technology to improve connections to the die; and a wafer-level encapsulation process. Like other wafer-level packaging technologies, this takes advantage of the economy of scale of batch processing, rather than dealing with individual chips in the packaging process.
Micron’s announcement of its Osmium technology describes the benefits for its product portfolio of memory devices and image sensors. Stacking of memory chips has been in high-volume production for several years, so this is a natural target for this next-generation vertical integration process. Combinations of memory chips and image sensors are also likely to be useful components in many imaging applications. Packaging subcontractors with recently developed image sensor and IC packaging businesses are likely to be challenged by this development.
NEC, another leading IDM, announced a new 3D system-in-package technology that also leverages wafer-processing expertise. Like Micron, NEC highlights three key technologies: a 50µm pitch bumping technology, a feed-through interposer for vertical connections between chips, and a wafer-based multichip assembly process. Interestingly, the multichip assembly process is also a derivative of the chips-first approach that Micron has resurrected. The chips are mounted onto silicon wafers with wiring layers added. These are then molded by resin and the wafer is removed. Again, this is a technology that relies on access to unpackaged die, which is an advantage for a large IDM.
These packaging developments from some of the leading IDMs in the industry are certainly noteworthy for their technology, but it is also interesting that packaging is increasingly a means for such companies to differentiate themselves and promote their status as technical leaders. Many competitive announcements from these companies are about 65nm products and other wafer-processing or chip design achievements, but more and more of them are about packaging. This is a sign that the convergence of chip and packaging that has been touted for years is being kept within the large IDMs. — J.D.