Panelists debate impact, challenges of “atomic” progression

by Ed Korczynski, senior technical editor, Solid State Technology

During SEMICON West 2006, a group of the industry’s top senior technologists came together to discuss the limits and possibilities for semiconductor material development. The technical seminar and panel discussion, sponsored by DuPont Semiconductor Materials, and moderated by this author, addressed material issues in the major International Technology Roadmap for Semiconductors (ITRS) initiatives.

One of the main themes of the panel discussion involved the ramifications of a clear shift toward dealing with individual countable atoms, a theme that carries into other parts of the industry — such as in lithography for topcoats on resist, atomic layer deposition for interconnect barriers, or transistor gate dielectrics. Panelists expressed a bit of anxiety, yet clear optimism about what kind of endgame does this trend lead to in terms of materials development, here’s what the panelists had to say.

While admitting that scaling to a level that requires counting individual atoms “terrifies us,” Dan Herr, director of nanomanufacturing sciences research, Semiconductor Research Corp., pointed out an array in which placing individual implant dopants gives new functionality not seen before. Incorporating nonlinear materials to add functionality is “a playground we haven’t played in yet, and I think it’s just the beginning of a whole new era,” he said. “So, I see it as a new frontier.”

Raj Jammy, director for front end processes, SEMATECH, added that this trend is really about “meticulous manipulation at the atomic level,” beyond just shrinking things down to ever smaller dimensions. “How do you get more functionality by trying to arrange or rearrange those atoms? I think that’s going to be the name of the game.”

Robert Havemann, VP of process integration, Novellus Systems, pointed out that counting individual atoms is already happening, noting that in ALD processes, throughput actually improves with further scaling because fewer cycles are required. Also, for interconnects, grain boundary scattering has been mostly resolved by optimizing the anneal to get very large grains and minimize electron collisions. “Sidewall scattering means we have to engineer the interface between the copper and the barrier much more carefully, and this is an atomistic engineering problem,” he said. Still, Havemann said that while he finds carbon nanotubes “to be very interesting” and will monitor their development through the SRC, he is “still pretty bullish” about the extendibility of copper.

Larry Thompson, president of Intellectual Property Services & Solutions LP (IPSS), and former director of advanced lithography and chemical engineering at Bell Labs, brought up a topic familiar to this industry, and one with keen interest to developers of leading-edge technologies seeking to avoid having the rug pulled out from under them (remember 157nm lithography?). He showed a graphic tracking historic aircraft speeds (see image, below), with a plateau just below supersonic speed — suggesting that while something is technically feasible, e.g., the Concorde, it may not be economically supported — e.g., higher fuel costs, unique and more expensive design/manufacturing costs, etc. Responding to an audience member, Thompson stated that “the Concorde of our industry is EUV lithography — if it has to be used. A $60 million tool that exposes 10 wafers an hour isn’t feasible.”

SEMATECH’s Jammy offered another perspective, pointing out that device scaling has gone on for years and has now arrived at atomic levels. The reason behind the scaling was purely economic — the smaller they are, the more we can fit, and the cheaper they become, he said. “Now perhaps the paradigm shifts in a different direction. If we’re frozen at a certain length or scale, how do you still make it cheaper? How do you manipulate, and how do you make that manipulation process cheaper? I think the scaling activity will continue in a different direction.” — E.K.

Next week WaferNEWS will present more discussions from the DuPont panel at SEMICON West, involving ideas for new materials business models.

What do you think is the “Concorde” of the semiconductor industry — or is there more than one?


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