Silicon Storage Technology (SST) announces a Z-scale package based on a serial flash with small and thin form factor. The package measures 0.4 &#215 3 &#215 3 mm, depending on chip memory density. As a wafer-level package, the Z-scale product uses multi-layer metal interconnect and routing technology. The interconnect system redistributes each chip’s bonding pads to external bumps. These bumps connect directly to the circuit board, or to another substrate.