A New Hierarchy for Electronic Interconnections

The hierarchy of electronic interconnections has undergone some significant changes over the last several years. In former times, lines were clearly drawn between the levels, which were defined as on the chip, chip-to-package, package-to-PCB, PCB-to-mother board, and system-to-system. However, with the sea change of IC packaging technology and the building tide of interconnection technology innovations, the old system no longer serves.

Jisso International Council (JIC), a technical and business group comprising Asian, European, and North American members, took on the task of developing a global consensus on terms. The JIC promotes a strategic partnership among organizations interested in the total solution for interconnecting, assembling, packaging, mounting, and integrating electronic system design. The mission is accomplished, in part, by providing a universally agreed upon set of terms, definitions, and approaches, which offer seamless interfaces and pathways to technological solutions between users and suppliers of electronic products.

Getting such a diverse group to agree is daunting, but at the 7th annual meeting held recently in Berlin, Germany, the council resolved that the job is done.

Level 0 – The Intellectual Property of an item pertains to the idea or intelligence imported or described in a formal document (protocol, standards, and/or specifications), design entity, or patent disclosure. The information may be in hard or soft copy and can include computer code or data format as a part of the descriptive analysis. Characteristics are described as to their physical, chemical, electrical, mechanical, electromechanical, environmental, and/or hazardous properties.

Level 1 – Electronic Element refers to uncased bare die or discrete components (e.g., resistor, capacitor, diode, transistor, inductor, fuse), with metallization or termination ready for mounting. It can be an IC, or discrete electrical, optical, or MEMS element. Individual elements cannot be further reduced without destroying their stated function.

Level 2 – Electronic Package is defined as a container for an individual electronic element (or elements) that protects the contents and provides terminals for making connections to the rest of the circuit. The package outline is generally standardized or meets guideline standards and may function as electronic, optoelectronic, MEMS, or system-in-package (SiP) and may in the future include bio-electronic sensors.

Level 3 – Electronic Module is an electronic sub-assembly with functional blocks comprised of individual electronic elements and/or component packages. An individual module would have an application specific purpose including electronic (including SiP), optoelectronic, or mechanical (MEMS), and generally provides protection of its elements and packages to assure the required level of reliability. The module may be a company standard (catalog item) or custom (OEM specific).

Level 4 – Electronic Unit refers to any group of functional blocks designed to provide a single or complex function needed by a system for it to serve a specific purpose. The electronic unit may comprise electronic elements, component packages, and/or application specific modules. The function of the electronic unit may be electronic, optoelectronic, electromechanical, mechanical, or any combination thereof, and in the future may include bio-electronic applications.

Level 5 – Electronic System is a completed, market-ready unit dedicated to combining and interconnecting functional blocks. The functional blocks can comprise electronic units, and may also include electronic modules, electronic packages, or elements. The electronic system can include the cabinetry – a backplane or motherboard into which the assemblies, modules, packages, or elements are inserted – and the cabling needed to interconnect the total functional block(s) into a configured system. It can vary in complexity.

While perhaps less “cut and dried” than the old approach, this new hierarchy reflects the realities and complexities of the present situation and helps to define a comprehensive framework and structure for harmonizing the global electronics manufacturing industry infrastructure. The concept has met with the approval of standards bodies such as the IPC, JEDEC, and JEITA and numerous companies in Asia, Europe, and the Americas; however, its success depends on the participation of everyone in the global electronics industry, beginning at the grass roots level. It is anticipated that the industry at large will openly embrace the concept. Comments and suggestions on Jisso are solicited and welcomed by the JIC. For more information, visit http://jisso.ipc.org.

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JOSEPH FJELSTAD, CEO and founder, may be contacted at SiliconPipe, Inc., 992 DeAnza Blvd., San Jose, CA 95129; 408/973-1744, ext. 203; E-mail: [email protected].


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