Chip-package Co-optimization

BY JOEL MCGRATH, Rio Design Automation, Inc.

The packaging engineer’s long-time lament is the challenge of an over-designed or too large chip. Additional functionality on the silicon as chip-process technology advance leads to higher I/O counts, running at higher speeds, and operating at lower voltages.

Package-aware I/O planning is an effective design strategy because a chip/package co-optimization helps enable “first-pass” success. Capabilities for a chip-package co-optimization tool are I/O synthesis, placement, and routing. I/O synthesis creates an optimized I/O plan combined with cost-effective packaging options, while satisfying physical and electrical constraints.

Chip-level I/O planning is generally done in isolation of the package or the rest of the system. This can lead to overly complex and even un-routable package designs that need multiple iterations to resolve. An alternate methodology uses package-aware chip design to enable chip designers to consider package routability, power delivery, and I/O behavior during the initial I/O planning process.

Defining Package-aware I/O Planning

Ideally, package-aware chip design begins early in the prototype phase and before floor planning. Trade-offs can be made without impacting the chip’s performance and establishing a “known good” I/O plan that is routable in the package and can meet cost targets. From this point, both chip and package design can proceed toward convergence as a unified entity rather than completely separate designs. After all, this is how the two design elements will exist when the design is complete – as a packaged device.

This methodology can be used across the spectrum of designs, accommodating small analog/mixed signal designs where rules-based I/O sequencing is more critical and pad-limited designs are common. It is useful for system-in-package (SiP) where chip-to-chip I/O planning must be coordinated simultaneously across multiple chips and the substrate. It can be also be used for high I/O count flip chip devices (Figure 1).

Figure 1. SiP interconnect.
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I/O planning must be part of the overall system design flow for silicon design teams to deal with package-related issues. Chip designers don’t need to be packaging experts, but packaging guidance should be built into their design tools, and they should understand some packaging concepts that have long been ignored.

Package-aware I/O planning can help chip designers optimize I/O placement to reduce die size and/or fully utilize the die area. It can help identify the least expensive package technology while ensuring that performance targets are met. Chip designers can get accurate estimates of load conditions to determine driver strength requirements and manage chip/package connectivity within the design environment, rather than externally in a spreadsheet. And, design groups can get realistic estimates of packaged chip costs.

Chip designers are often surprised by the complexity of system-on-chip (SoC) packages. A typical 2000-pad flip chip SoC has 6-12 layers containing an intricate escape pattern of interconnects and vias. Unlike silicon design rules, package design rules are flexible and a package designer can decrease the interconnect pitch to fit more routes in congested areas, though the finer pitch tends to reduce manufacturing yields.

An early I/O and package plan enables chip designers to begin analyzing the entire interconnect, from the chip’s I/O buffers to the PCB (Figure 2). Timing and signal integrity data provide a basis for defining chip and package design constraints. Chip designers can work with real-world system characteristics and avoid over-constraining the chip design. The use of realistic constraints helps create designs that are routable, while minimizing both costs and design cycles. I/O planning allows for discovery of the minimum die size possible via optimized I/O and bump placement, combined with the most cost-effective package option.

Figure 2. I/O driver to PCB interconnect.
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Although synthesis, placement, and routing are the main tool functions needed for I/O planning, the methodology also requires a user interface for collecting and managing I/O data in a bump/BGA map. The I/O planning interface acts as a dynamic repository that always shows the correct state of the I/O plan.

Synthesis and placement begin the I/O plan by creating a correct-by-design I/O ring that satisfies a set of constraints, including signal/power/ground (SPG) requirements, package design rules, the core floorplan, and board-level I/O requirements. To meet the SPG requirements, synthesis must consider both signal- and power-integrity factors, including the power and ground needs of I/O drivers (Figure 3). The tool must calculate the current requirements of a particular voltage plane based on the driver models, then calculate the number of balls needed to meet them. For designs with multiple voltage domains, synthesis must accommodate the needs of each.

Figure 3. Signal/power/ground ratio per voltage domain.
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These main functions are supported by the ability to analyze timing, power, and signal integrity. These functions must work with industry-standard data files (DEF and LEF, for example) and tool interfaces. To enable simultaneous representation of the entire chip and package, the I/O planning environment needs a unified data model, which is represented in a common database. In addition to providing the basis for optimizing an initial I/O plan for the chip, this model helps resolve I/O-related questions throughout the design flow. At any point in the flow, chip designers can interactively see the consequences of any I/O changes to the chip floorplan.

Figure 4. Unified data model.
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Package-aware chip design faces many challenges that cross various disciplines, beginning with a unified data model that can support both chip and package as active components in a single user interface (Figure 4). The unified data model provides the ability to explore tradeoffs on both chip and package with immediate feedback, including a complete understanding of electrical and physical chip and package constraints. The solution also needs to function within existing design flows and support industry-standard formats such as LEF/DEF on the chip side and APD on the package side. Because signal and power integrity are critical to the success of any packaged chip, the tool should also be able to evaluate the electrical performance as part of the prototype flow. Because the tool is operating in a planning environment where all the data may not be present and the design is incomplete, the extraction and analysis tools need to be flexible. They also need to be smart enough to account for these limitations, while still providing accurate enough results to be useful. And finally, package-level routing and voltage domain plane cutting needs to be design-rule-check (DRC) clean and abide by packaging rules. This is critical in establishing valid chip-to-package net assignments and proper power plane bump/ball assignments.

Chips being designed today must be made in the context of the package. Companies sell packaged devices, not bare chips. Without a package-aware chip design capability, designers are blind to the rest of the system.

JOEL MCGRATH, technical marketing manager, may be contacted at Rio Design Automation Inc. 2901 Tasman Dr. Suite 112, Santa Clara, CA, 95054-1137; 408/844-8038; E-mail: [email protected]


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