NEC debuts 55nm embedded DRAM

September 13, 2006 – NEC Electronics says it has applied its new 55nm process to CMOS-compatible embedded DRAM technology, an enhancement to its metal-insulator-metal (MIM2) technology, combining hafnium silicate film and nickel silicide to reduce power consumption and leakage current, and improve on-current by as much as 20%. Earlier this summer, NEC tipped its initial work with 55nm standard CMOS process technology, a shrink of its 65nm process, which it said achieves 1/10 the power consumption in standby mode of conventional 65nm devices, and boosts on-current by 20%-30%.

The new process employs both a cylindrical-type stacked capacitor structure, to ensure high yields, and a low-temperature MIM2 capacitor with a zirconium oxide (ZrO2) high-k dielectric material, to enable better storage capacitance in the eDRAM’s smaller bit cells. Unlike NEC’s commodity DRAM process, the eDRAM process uses the same structure as its standard CMOS process, minimizing the number of extra process steps and reducing turnaround time.

Using nickel silicide helps maintain low parasitic resistance of the scaled-down eDRAM cell and peripheral circuits, and also reduces standby and operating power, according to NEC. The eDRAM cell transistor exploits the work-function modulation effect of the high dielectric constant (high-k) to reduce transistor channel concentration, boosting performance, reducing leakages, and suppressing variability.

Meanwhile, introducing hafnium silicate film also allows NEC to continue to use polysilicon gates as opposed to metal gates, further reducing process risks for volume production.

The eDRAM can be applied to system-on-chip (SoC) devices for cell phones and handheld devices, as well as consumer devices such as gaming consoles, according to NEC, which expects to achieve volume production of 55nm 8Mb-and-larger embedded DRAM macros by 1H07.

“By delivering the only CMOS-compatible eDRAM at the 55 nm node, NEC Electronics is enabling designers to overcome the limitations of embedded SRAM and discrete DRAM components to achieve high-performance SOCs for next-generation applications,” said Takaaki Kuwata, GM of NEC’s advanced device development division, in a statement.


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