September 18, 2006 – Qimonda AG and partner Nanya Technology Corp. have qualified their 75nm DRAM trench technology, as well as a 512Mbit DDR2 memory chip build on the platform, with minimum structure sizes down to 70nm. The devices were developed at Qimonda’s R&D centers in Germany, and volume production has already commenced at Qimonda’s 300mm DRAM line in Dresden.
The 75nm process targets high performance and high-density applications such as DDR3 and graphics products, with densities including 1Gbit-2Gbit DRAM, according to Thomas Seifert, manager, market and operations at Qimonda, and Pei Lin Pai, VP of global sales and marketing for Nanya, in a statement. The process has been qualified to meet JEDEC performance requirements for use in high-end server and computing applications, the company noted.
Pai noted that the new process also offers a more competitive cost structure, increasing potential chip output/wafer by about 40% vs. Qimonda’s 90nm process.
“With the qualification of our 75nm DRAM Trench technology and the first product we have reached an important milestone on our technology roadmap,” stated Seifert.