BY ZHIHONG CHEN AND JOERG APPENZELLER, IBM
Current technology uses field-effect transistors (FETs) with feature sizes smaller than 100 nanometers that start to show some device degradation due to short channel effects. Methods such as higher doping concentration in the channel and silicon-on-insulator (SOI) have provided temporary solutions, but will face limitations when the device channel length is further reduced.
The diameters of single-wall carbon nanotubes (SWCNTs) vary between approximately 1 and 3 nanometers, fitting into the ultra-thin body category. The limited phase space for scattering events in this one-dimensional system results in near-ballistic transport conditions in SWCNT devices even at room temperature. These advantages have triggered interest in exploring nanotube-based electronics that will enable aggressive channel-length scaling without the introduction of short channel effects and mobility deterioration for higher device speed and density, and lower power consumption. The next step is to implement circuits on individual nanotubes to take best advantage of the smallness and evaluate whether the device advantages translate into a better circuit performance. The question is whether a new concept to build completely different electronics is needed or can we still take advantage of Si technology and replace the channel material with CNTs?
 SEM picture of a 5-stage CMOS-type single carbon nanotube ring oscillator. |
Current Si CMOS logic comprises p-doped FETs (p-FETs) and n-doped FETs (n-FETs). Doping in the channel is used to control the threshold voltages. This scheme cannot be used for CNT FETs in which the channel is kept undoped. Rather, a novel gate metal work function control is used to adjust the threshold voltages of the p- and n- type CNT FETs. Palladium (Pd), with high-work function, is used as a gate for the p-FET, and aluminum (Al), with low-work function, is used for the n-FET. The impact of the Al gate on an n-FET is compared with a Pd gated n-FET. For a 15-nm thick atomic layer deposited Al2O3 dielectric and a 2-nm wide SWCNT, the threshold voltage measures around +2V for the Pd-gated device and +0.4V for the Al-gated device. The conclusion of the experiment was that the low-work function Al gate can shift the threshold voltage of the n-FET by -1.6V. For a Pd gated p-FET fabricated on the same nanotube with the same device geometry, the threshold voltage is found to be around -0.8V. Therefore, the threshold voltage difference between the Pd gated p-FET and the Al gated n-FET is 1.2V. The shift of threshold voltages with the use of the proper metal gates is the key to fabricating a pair of p- and n- FETs to form a CMOS type, nanotube-based inverter.
The results presented here are the first demonstration of a 5-stage ring oscillator fabricated completely on a single semiconductor carbon nanotube. Figure 1 shows 12 FETs side by side located on top of a nanotube, the source/drain metal contacts locally pin the potential down and virtually “cut” the nanotube into 12 independent segments. Here, 10 of the FETs form the 5 inverter stage ring oscillator, while the other 2 FETs form another inverter stage, which is used as a read-out stage to prevent any interference from the measurement set up to the ring oscillator. A spectrum analyzer is used to record the Fourier transform of the oscillation at different supply voltages. At a voltage of 0.56V the oscillation occurs at 18 MHz, and the frequency increases to 72 MHz at a voltage of 1.04V, with a corresponding stage delay time of 1.4ns. The increased frequency is a direct result of the increase in current through the FETs with increasing bias. From the DC characteristics of the CNTFETs, terahertz (THz) performance has been predicted. The demonstrated single CNT ring oscillator to date has the highest frequency performance; however, it is still orders of magnitude away from the theoretical prediction. The parasitic contribution from the circuit layout is much larger than the intrinsic capacitance of the nanotube, which is estimated to be few attofarads. Therefore, the performance of our ring oscillator is dominated by the parasitics rather than any intrinsic nanotube properties. Optimization of the circuit layout to eliminate these parasitics will improve the oscillation frequency and may eventually be able to reveal the intrinsic AC performance of SWCNTs.
REFERENCES
Journal of Science, Vol. 311, 1735 (2006)
ZHIHONG CHEN and JOERG APPENZELLER, research staff members, may be contacted at IBM T.J. Watson Research Center, Yorktown Heights, NY 10598; 914/945-2703; E-mail: [email protected]; [email protected].