October 2, 2006 – Cadence Design Systems Inc. has announced what it calls a “lithography-aware” design flow that links resolution-enhancement technologies (RET) with physical design and verification.
The flow addresses critical lithography-induced yield problems by allowing users to use the same models throughout the flow (design phase, implementation, and manufacturing), e.g. combining automated layout optimization with advanced manufacturability models in design phases. It will be used for Cadence’s Encounter digital IC design platform, as well as third-party design-for-manufacturing (DFM) products.
The design flow was built in collaboration with Brion Technologies and Clear Shape Technologies, and will link to those companies’ DFM and computational lithography technologies, providing “an integrated lithography modeling, design implementation, and layout optimization flow,” the company said in a statement.
“We’ve defined an interface that links both internal and external lithography modeling and verification technologies with our design and implementation solutions,” stated Wei-Jin Dai, corporate VP at Cadence, adding that the technology targets designs ranging from 65nm to 32nm processes.
Brion and Cadence have been working for months to define a litho-aware design flow to link signoff quality OPC and OPC verification with design stage layout optimizations, stated Shauh-Teh Juang, SVP of marketing and business development at Brion. Clear Shape CEO Atul Sharan added that the links “provide designers a plug-in solution that bridges design and manufacturing.”
Shuichi Inoue, GM of NEC Electronics Corp.’s process technology division, a customer of both Brion and Cadence, stated that the collaboration “enables a lithography-aware design flow that correlates well to the mask-making and manufacturing stages,” adding that NEC will provide requirements and directions for this effort.”
Greg Buchner, VP of engineering at ATI Technologies Inc. which uses Clear Shape’s InShape tool for predicting hot spots during the physical design phase, said that the combination with Cadence’s Chip Optimizer helps to “prevent costly and time-consuming iterations that rely on detecting lithography problems after tape-out or, even worse, in silicon.”