Consortium to develop cost-effective 3D interconnects

October 12, 2006 – A list of equipment providers, materials companies, and researchers have joined to create an international consortium to address technical and cost issues of creating of thru-silicon-via (TSV) 3D chip interconnect, for use in chip stacking and MEMS/sensor packaging.

The Semiconductor 3D Equipment and Materials Consortium (EMC-3D) will develop processes for creating micro vias between 5-30 microns on thinned 50-micron 300mm wafers, using both via-first and via-last techniques. Major processes being integrated into the EMC-3D program include via etch and laser drill; insulator/barrier/seed deposition; micro via patterning with RDL capabilities; high aspect ratio Cu plating; carrier bonding; sequential wafer thinning; backside insulator/barrier/seed deposition; backside lithography; backside contact metal plating; chip-to-wafer placement and attach; and dicing.

In addition, wafer-to-wafer attach, dicing and de-bonding will also be demonstrated. Cost of ownership goal for the integrated 3D process is $200/wafer.

Equipment companies initiating the consortium include Alcatel, EV Group, Semitool, and XSiL, with materials companies Rohm and Haas, Honeywell, Enthone, and AZ, and wafer service support from Isonics. Research partners include Fraunhofer IZM, SAIT (Samsung Advanced Institute of Technology), KAIST (Korea Advanced Institute of Science and Technology) and Texas A&M U.


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