Oct. 11, 2006 — A new consortium, EMC-3D, has been created to address the technical and cost issues of creating 3D interconnects using Thru-Silicon-Via (TSV) technology for chip stacking and MEMS/sensors packaging.
Several major equipment manufactures have joined with material companies to work with key research groups to address the issues of cost-effective manufacturing and integration. Equipment companies initiating the consortium are Alcatel, EV Group, Semitool and XSiL.
Associate research members include Fraunhofer IZM, Samsung Advanced Institute of Technology, Korea Advanced Institute of Science and Technology and Texas A&M University. Material members include Rohm and Haas, Honeywell, Enthone, and AZ with wafer service support from Isonics.
The consortium will develop processes for creating micro vias between 5 and 30 microns on thinned 50 micron 300mm wafers using both via-first and via-last techniques.
Major processes being integrated into the EMC-3D program are via etch and laser drill, insulator/barrier/seed deposition, micro via patterning with RDL capabilities, high aspect ratio Cu plating, carrier bonding, sequential wafer thinning, backside insulator/barrier/seed deposition, backside lithography, backside contact metal plating, chip-to-wafer placement and attach, and dicing.
In addition, wafer-to-wafer attach, dicing and de-bonding will also be demonstrated. Cost of ownership goal for the integrated 3D process is $200 per wafer.