by M. David Levenson, Senior Technical Editor
The long-suffering mask making industry is presently in fine shape, according to experts at the 26th Annual BACUS Symposium on Photomask Technology in Monterey, CA, Sept. 18-22, sponsored by the SPIE. Gil Sheldon reported in his annual industry assessment that the growth rate of the photomask segment was 6.8%, roughly half of the semiconductor industry’s 11.1% growth rate, even though the number of plates shipped (700,000) remained constant. Average yield was quite high (over 95%), and most obvious failure modes were being successfully addressed. The one cautionary item was a 10x reported increase in returns of mask plates due to growing (progressive) defects for reticles intended for 193nm exposure. On balance, the $3.8 billion photomask industry continued to successfully support the $253 billion semiconductor industry.
What the photomask industry cannot support is R&D by its own equipment suppliers, according to Michael Lercel, director of lithography at SEMATECH. Maskmaking equipment constitutes only an $800 million/year industry segment, and even devoting just 15% of revenue for R&D, it could only afford to introduce a new generation of equipment every six years — vs. the two-year rate required by the International Technology Roadmap for Semiconductors (ITRS). Thus, the development of specialized maskmaking equipment, such as repair tools, has to be subsidized by the larger industry through institutions like SEMATECH. Other mask fabrication machinery can be adapted from that used in the larger wafer fab industry. Several speakers pointed out the coming unfeasibility or impossibility of making the 4X masks required for 45nm and 32nm nodes using plausible extensions of today’s very slow e-beam mask writing technology. No similar tool is widely employed in wafer fabs.
While a few new hardware tools were launched at BACUS (notably the Zeiss AIMS 45-193i aerial image inspection system, capable of NA=1.4 and polarization simulation), the emphasis has visibly shifted to software and data handling, as the EDA community has become more prominent. Invarium Inc. decloaked to reveal its Dimension 45/32 proximity correction suite, which claims to enable process windows comparable to immersion with dry exposure tools. Brion unveiled its Tachyon M3D, which it says improves high-NA modeling by incorporating heuristics derived from EMF simulations. Synopsys announced an alliance with Nikon to incorporate real-world parameters of Nikon exposure tools in Synopsys EDA modeling.
While EUV remains a possibility for the future, and EUV maskmaking technology continues to improve, the consensus is that 193nm will continue to be the wavelength of choice for production. Thus, continuing the progress implicit in Moore’s law means achieving sizes and densities beyond seemingly impenetrable physical limits. Immersing the wafer in water during exposure does that — raising the maximum numerical aperture of the lens to ~1.35 and reducing pitch to ~75nm — but it implies a pitch on the 4X reticle as small as 300nm.
Bob Gleason of Intel catalogued the many problematic new phenomena that occur in such a regime. For example, the optimum phase shift for a PSM becomes different for different polarizations, and can also be a strong function of pitch — in particular, resonances occur when the pitch becomes an integral number of wavelengths. One audience member suggested that immersion had drowned alternating-PSM technology, which should be abandoned in favor of dual dipole illumination with polarization control and simple chrome on glass masks. That, of course, has its own problems and costs. Christophe Pierrat and a team from the AMTC in Dresden reported related contrast-loss effects for CPL masks, suggesting that only trench type masks and not mesa-types could be used successfully for the finest features.
Another approach to extending 193 exposure technology is to replace water with a high index fluid, but keynote speaker Martin van den Brink of ASML held out little hope of that. Instead, he and several others touted the potential of double processing technology (DPT), in which two resist patterns are overlaid on one another (using a hard mask) to fabricate a single layer. Van den Brink even showed several 64nm pitch logic-like patterns fabricated in this way — an accomplishment not scheduled until the 22nm node.
However, doing that was very difficult, as several subsequent speakers noted. Bob Naber detailed many of the difficulties in a paper authored by a team from Cadence and ASML. While gates oriented in the same direction can be printed with k1<0.2 using double patterning and dipole illumination, the perpendicular field poly shapes have to be carefully fractured in order to print and connect properly. Thus, decomposing the design into the two (or more) masks needed for double patterning technology and applying appropriate resolution enhancements still remains more art than science. Placement errors, perhaps combined with focus and exposure excursions, can lead to feature breaks, jogs, etc., narrowing a multi-dimensional process window, yet to be fully explored.
Jong Gul Doh of Samsung attempted to capture the mask fabrication challenges in double patterning, in which overlay and registration errors become as critical as CD uniformity and mean-to-target. In registration, 58% of the errors appear due to stage randomness and only 25% due to global mask registration issues, according to Doh. ASML’s Jung Chul Park explored the mask error enhancement factor (MEEF) and stitching error issues in two double patterning methods, reporting that MEEF is best in the positive tone CLN process and recommended the use of CPL masks. However, he warned that the short lines needed for proper stitching the two patterns together have lower k1 than the final pattern, and are subject to line-end pullback and other distortions.
A team from DNP presented a new and fairly scary explanation for the progressive defects and haze found to limit the lifetime of masks used for 193nm exposure. These defects appear mostly as crystals of ammonium sulfate growing on the surface of the mask even under the pellicle. According to this new theory, these defects appear once the concentration of ammonium sulfate on the surface gets large enough for aggregation sites to become stable. Once that threshold is crossed, damaging defects grow quickly. In spite of all the efforts to control ammonia in litho environments, there is always more than enough for the haze-forming reaction. The rate limiting input is sulfate (S0x), which is present in average mask storage environments at a 0.13ppb level. According to DNP, that implies a 40-day storage lifetime, even for masks cleaned without the use of sulfuric acid. Low sulfate atmospheres slow the growth of haze while UV exposure has little effect. They recommend a sulfate level below 0.01ppbV if masks are to be stored for a year without damage.
Other yield problems for advanced chips result from discrete “hot-spots” on the mask, where the optical proximity correction treatment has created (or at least failed to solve) problems, even though the design is “clean” according to the design rule check. According to Mark Mason of Texas Instruments, everyone working at the leading edge must use post-OPC verification (POV) tools to catch geometries that produce “evil pupil fills.” Such geometries are more complex than the line-space patterns typically used in OPC models. The problem has been that running a full chip design to find the rare “hot-spots” that print badly (and often only in some portion of the focus exposure window) was quite time consuming. The alternatives to POV systems, however, amounted to “faith-based lithography” or running split lots, which took even longer. Mason reported that modern grid-based POV systems can now verify the mask pattern more rapidly than it can be FTP-ed to the mask shop. — M.D.L.
Next week’s WaferNEWS will examine BACUS’ Friday session, which discussed the industry’s progress and remaining challenges in DFM — and whether everyone fully understands how difficult DFM will be.