IMEC: Double-patterning immersion works for 32nm

October 19, 2006 – IMEC and ASML claim they’ve proven that double-patterning 193nm immersion lithography (NA=1.2) can be a viable interim solution — at least technically — for flash and logic manufacturing at the 32nm node, until extreme-ultraviolet (EUV) lithography achieves production-ready levels.

The “very promising results” involved splitting gate levels of 32nm half-pitch flash cells as well as logic cells in two complementary designs, and receiving optical proximity corrections and a classical “litho-etch-litho-etch” approach, according to IMEC. ASML’s XT:1700i immersion scanner, delivered in late September and is expected to be accepted later this month, will be “the workhorse” for the double-patterning work. Future research will focus on improving the overlay to make the process reproducible.

Meanwhile, IMEC claims it has made “significant progress” with ASML’s EUV alpha demo tool, delivered in mid-August, with work ongoing to integrate the Carl Zeiss projection optics box and Philips Extreme UV light source (since identified as a low-power xenon source, rather than tin). A TEL Clean Track Act12 is also under installation.

Other work IMEC is touting, ahead of its Annual Research Review Meeting next week:

— Development of the world’s first functional analog and RF circuits — a two-stage opanp (50dB gain, 2-8GHz tunable oscillator) — using FinFETs with a metal-gate high-<>k gate stack and 45nm gate length transistors. FinFETs have higher intrinsic amplification thanks to a better control of the short-channel effects, although maximum cutoff frequency (100GHz) is still ~3x lower than planar bulk CMOS, due to the fins’ series resistance and lower mobility at the sidewalls. Future work will focus on increasing the speed of the FinFETs by increasing mobility, decreasing relatively large series resistances and/or decreasing extrinsic capacitors between the gate and drain. A bulk FinFET option also is being researched.

— Copper-top interconnect process technology, a low resistance, post-passivation interconnect
module, has been transferred to National Semiconductor’s production facility in Malaysia, the result of a three-year collaboration between National SEMI and IMEC’s thin-film technology group. The Cu-top technology uses Cu plating in a photoresist pattern to achieve a small linewidth, enabling a high-density high-current interconnect layer. The contacts through the 2µm thick IC passivation have a diameter of only 3µm, with “very good contact resistance between the plated Cu and the underlying Al layer,” IMEC claims. The Cu layer on the chip is protected by a 10µm thick polymer dielectric layer, which is photo-defined to clear scribe lanes and bonding pads. The Cu bonding pads are covered with an Al metallization to allow for testing and wire-bond packaging. IMEC and National Semi are currently developing a significantly thicker version of the technology, to further reduce sheet resistance and thus achieve higher-power analog circuits.

— A reconfigurable processor for video decoding, 6-12x more power efficient than state-of-the-art C-programmed processors, built from IMEC’s ADRES (architecture for dynamically reconfigurable embedded systems) architecture template using a corresponding compiler. The processor can support multiformat MPEG-2, MPEG-4, and H.264/AVC video decoding at resolutions ranging from QVGA up to D1, with demonstrated 30 frames/sec H.264/AVC video decoding at CIF resolution by means of an FPGA implementation. This result was achieved in collaboration with partners Samsung and Freescale, with support from Barco Silex.

— IMEC is merging its multidisciplinary research for “More Moore” into a single operational entity starting in January. The group, headed by new COO Luc Van de hove, will combine conventional CMOS base processes (130-90nm) of IMEC’s 200mm pilot line additional process modules and devices. Processes will be transferred to IDMs and foundries. IMEC already works with European partners in the “More Moore” research focusing on 32nm and below CMOS scaling. “With this reorganization, we will further develop critical mass in both ‘More Moore’ and ‘More than Moore’ research areas and ensure that both research domains are sufficiently integrated and interlinked,” said Gilbert Declerck, president and CEO IMEC, in a statement. “Our successful core partnership program on (sub-)32nm scaling will proceed at the same world-class level in our 300mm clean room. In addition, we will give momentum to our ‘More than Moore’ research anticipating the changing market.”


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