Semiconductor manufacturers face critical challenges at the sub-90-nm nodes, such as increased costs, shorter cycle times and improved yields, and optimization of expensive production and lab equipment. Development challenges for the semiconductor industry today result from tighter geometries, new materials, and the introduction of new transistor architectures. These changes increase the difficulty of semiconductor analysis for yield enhancement (YE) and failure analysis (FA). New analysis schemes and methodologies are being implemented for ramp and production control and lab FA, circuit edit (CE), and debug.

By Julia Goldstein, Ph.D., contributing editor