SEMATECH gate-stack symposium eyes post-45nm strategies

October 9, 2006 – Participants at the recent 3rd Annual International Symposium on Advanced Gate Stack Technology have narrowed their consensus about their strategies for implementing high-k/metal gate stacks in 32nm- and beyond process technologies.

Among the discussions at the event, hosted by SEMATECH and co-sponsored by IEEE, was a panel debate over fully silicided (FUSI) gates vs. a dual-metal gate approach. Consensus was that despite attractiveness for FUSI in some applications, there are more significant limitations in high-performance implementations and high-volume manufacturing than with dual metal gates.

Symposium participants also discussed nMOS metal gate electrode materials, which are now yielding an effective work function close to that of doped polysilicon gates, and are no longer deemed a critical issue. However, pMOS metals remain problematic, due to threshold voltage roll-off in scaling the dielectric thickness, as illustrated by findings from Freescale and SEMATECH.

Several speakers presented work being done on Ge and III-V alternative channel material devices, and although progress is being made, there was general acknowledgement among Symposium attendees that this area will require more effort and more resources to demonstrate manufacturable solutions.

Keynote speaker T.P. Ma from Yale’s Department of Electrical Engineering discussed three electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects associated with high-k gate stacks, including inelastic electron tunneling spectroscopy, pulse agitated substrate hot electron injection, and charge pumping.

Other findings disclosed at the Symposium:
– Jack Lee, U. of Texas/Austin, outlined electrical and materials characteristics of MOS capacitors and MOSFETs on III-V substrates, with varying ratios of silicon and germanium in interface passivation layers;
– Y. Nara from Selete demonstrated dual workfunction full metal gate devices consisting of tungsten stacked on workfunction control metal layers; and
– J. Robertson from Cambridge U. described the fundamental mechanisms of defect passivation by fluorine.

SEMATECH plans to publish full papers from the Symposium by Feb. 2007.

“It’s clear that we need to work collaboratively on fundamental issues of materials science if we are to stay on the roadmap to scale CMOS transistors and achieve manufacturable results in the next decade,” said Symposium Chair Hsing-Huang Tseng, also SEMATECH’s FEP division chief technologist and CMOS Extension program manager, in a statement.


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