SiP Methodology Addresses Noise Issues

The impact of dynamic power noise on system behavior is key for SiP designs where multiple ICs share one package and one substrate, claim the companies. If provided with accurate data on the IC’s power network and switching noise, SiP designers can analyze a system’s power delivery and optimize IC-package-PCB designs. Akira Denda, department manager of the full custom ASIC division, 1st systems operations unit, NEC Electronics, noted that the methodology developed with Apache is useful because identifying issues after silicon tapeout is challenging and expensive.

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