November 2006 Asian Exclusive Feature 1:

Fujitsu reports progress towards carbon nanotube interconnects for 32nm

Development of carbon nanotube (CNT) interconnects for the 32nm node is starting to make major strides. Though CNTs could potentially carry the high current densities required for next generation interconnects, it has proved difficult to grow them at low enough temperatures with the right properties, particularly with low enough resistance. Now, Fujitsu Laboratories Ltd. has demonstrated selective growth of vertical bundles of carbon nanotubes in 40nm via holes uniformly across 300mm wafers at temperatures around 450°C, and with resistance as low as tungsten — edging closer to the target of matching the resistance of copper at CMOS-compatible growth temperatures of 400°C.

CNTs are one of the few materials likely to have the potential current density reaching the 1 x 107A/cm2 that the ITRS says will be needed for circuits at the 32nm node. Ballistic conduction within the tubes, without scattering, should mean lower resistance than copper circuits. And CNTs could likely be grown easily in very small via holes with very high aspect ratios, without the problems that complicate copper deposition at extreme geometries. First use is likely to be for vertical interconnects in vias at 32nm, followed by horizontal circuits in the 22nm generation.

By depositing a uniform catalyst selectively only in the via holes, and using a hot-filament CVD process, the researchers made an array of vias with some 1000 CNTs in each 2-micron hole across the wafer (figure 1, above). Key to obtaining high current density and low resistance from the interconnect were making individual CNTs with low resistance, growing a high density bundle of tubes in each via, and improving the ohmic connection between the tubes and the copper layer underneath.

CNTs with atomic structure that makes them act like metals have the lowest resistance, but they are difficult to grow. The larger the diameter of semiconducting-type multiwalled CNTs, however, the narrower their band gap, and the conductivity of these large diameter tubes can approach that of metal. The diameter of the CNT is largely determined by the size of its catalyst. So instead of the usual catalyst thin film layer — with its random scattering of catalyst clumps of different sizes that can’t be well controlled — Fujitsu researchers selectively deposited Co nanoparticles of the desired size directly in the bottom of the via holes. This also allowed them to put dense concentrations of catalyst in each via to grow more fibers.

The process for making and depositing these precisely sized nanoparticles efficiently in volume across the wafer involved creating the particles by hitting a cobalt target with a laser, then blowing them into an impact plate to quickly sort out 4nm particles by their inertia. This process is about 1000x faster than the usual approach of sorting high-density nanoparticles according to their electrostatic force with a differential mobility analyzer, making it practical for 300mm wafer volumes. The high-density particles are difficult to charge, but because this impact approach uses mass instead of charge, it works with all the uncharged particles too, netting a much higher proportion of usable particles. To selectively deposit the particles in the bottom of the via holes, Fujitsu researchers sucked them from the high-pressure chamber where they’re created (in a 1000Pa He atmosphere), down into the high vacuum (10-3Pa) chamber where they’re deposited, forming a focused particle beam that shoots into the wafer. That enabled deposition of particles evenly at the bottom of via holes as small as 40nm in diameter.

Finally, to prevent oxidation while the wafer is being moved between chambers, which increases resistance, they used TiN instead of Ti to improve the ohmic connection to the copper layer underneath.

Using these techniques, Fujitsu scientists claim to have demonstrated resistance of 0.59 Ω in 2-micron CNT vias, matching the resistance of tungsten plugs, lower than has been reported for other CNT interconnects to date. The vias handled current density of 2~3.2 x 106A/cm2 for more than 100 hours at room temperature without degradation. CNT density within these vias was about 1011 tubes/cm2, and increasing this density by a factor of ten should bring resistance down to about that of copper. Fujitsu says it’s already begun to grow CNT bundles in 40nm vias with densities close to 1012 tubes/cm2.

CNT interconnects would also need to be grown at CMOS compatible temperatures, be planarized by CMP, and be grown horizontally as well as vertically. To integrate the interconnect with dielectric, and especially low-k dielectrics, process temperatures need to held to 400°C or less. Fujitsu says its circuits with 0.59 Ω resistance were made at 510°C, and the company has grown CNTs at the desired 400°C temperatures, but they are of lower quality, and have higher resistance. The next step will be improving the current CVD process, and exploring lower temperature ones (see figure 2, below).

The CNTs can be planarized by conventional oxide CMP, as the tubes are securely attached enough tow withstand polishing at changing speeds. Fujitsu says it will next work on improving their stability under chemical planarization for better control. And finally, though still in an exploratory stage, bundles of CNTs have been grown horizontally on the wafer from a block of catalyst. — Paula Doe, Contributing Editor, Solid-State Technology and Yuji Awano, research fellow, Fujitsu Laboratories Ltd., and program manager, MIRAI-Selete carbon circuit program, SST partner Nikkei Microdevices

Fig. 1 (above): ~1000 carbon nanotubes grown in each 2µm-diameter via hole across the 300mm wafer, using hot-filament CVD. (Source: Fujitsu, Fujitsu Laboratories)

Fig. 2 (below): Higher densities of carbon nanotubes per via have brought resistance down to that of tungsten, and researchers figure further improvements in growth density should bring performance close to copper. The temperatures needed to grow high quality CNTs with lower resistance are also dropping, getting close to the 400°C level needed for CMOS integration. (Source: Fujitsu and Fujitsu Laboratories)


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