Brion, Japan’s TOOL pledge IC litho integration

January 18, 2007 – Brion Technologies Inc. and Japan’s TOOL Corp. have agred to combine TOOL’s LAVIS layout visualization platform with Brion’s Tachyon OPC and RET/OPC verification system, in a bid to help users more easily obtain litho simulation results without difficult and complex data preparation.

The deal combines LAVIS’ large-volume data handling and high-speed data display capabilities with Tachyon’s ability to execute high-speed, full-chip simulation and inspection with high precision, the companies said.

Brion’s Tachyon performs high-speed, accurate simulation to verify design data and OPC data during the design process, but the complex, aggressive OPC patterns being incorporated into leading-edge designs can result in skyrocketing volumes of design data, the company explained. Integrating TOOL and Brion’s platforms enables repeated high speed simulations and verifications to address hot spots and parameter alterations, as well as data modifications, bringing about substantial improvement of design verification turn-around time, they said.

“TOOL and Brion’s integrated design environment is most welcome,” said Hiroshi Sakuma, GM of NEC Electronics C, noting that being able to perform high-precision lithography simulation easily and repeatedly through LAVIS’ design environment will be “critical to solving problematic hot spots.”

In addition to the stated benefits, the pact with TOOL also gives Brion’s parent company, litho toll supplier, a new foothold in Japan. It also may help designers do something useful (and faster) with their design data — other companies have tried to get realistic images of structures as manufactured onto the CRT screens of designers, but have encountered various problems, including speed and figuring out what to do with the data.


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