HP’s crossbars pay off three nodes early

by Ed Korczynski, Senior Technical Editor

On a beautifully grey Winter Solstice day in Palo Alto, CA, SST/WaferNEWS editors got a peek at HP’s “crossbar array” technology, once considered for far future memory and logic, but now seen as a new 15nm-width field-programmable nanowire interconnect circuit that may see production in 2010 along with 45nm node technology — three nodes earlier than anyone expected.


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