January 29, 2007 – Touting “a significant breakthrough in transistor technology,” Intel Corp. says it has progressed its 45nm process technology from a SRAM test chip unveiled in Jan. 2006 into a working 45nm transistor — devices that incorporate a hafnium-based high-k dielectric material and a new combination of metals for the transistor gate electrode. The new “Penryn” transistor will start shipping in volume by year’s end on various systems, including those with Microsoft Vista OS.
“These are not lab devices, not just research results,” said Mark Bohr, Intel Senior Fellow, in a conference call presenting the details of the 45nm process. “We have both NMOS and PMOS, providing better performance and lower leakage,” and the chips are “manufacturable in high volume,” he said, adding that the performance specs are “better than our competitors, including those using SOI.”
Work on high-k and metal gates (HK+MG) has been presented in conference papers for several years from various chipmakers, Bohr conceded, but most describe early results with suboptimal performance characteristics and only for one device type (either NMOS or PMOS), much less putting everything together into an integrated CMOS process flow, with working processors at or nearly ready for manufacturing in volume.
He also noted that the Penryn 45nm processor utilizes the same features, interconnects, high-k features, and design rules as the 45nm SRAM test chip the company revealed last January (0.346 µm2 cell, 153 Mbit density, 119 sq. mm chip size).
The new 45nm technology promises 2X increased transistor density, ~30% reduction in transistor switching power, 5X reduction in source-drain leakage power and >10X reduction in gate oxide leakage power. The reduction in gate leakage results from the fact that the gate oxide thickness can be increased using this hafnium-based high-k dielectric, which is produced by atomic layer deposition (ALD) — though Intel did not indicate what type of ALD was used (ternary or quadrinary alloying elements, or amorphous vs. crystalline phase) or what any integration challenges were.
Bohr showed a TEM micrograph (see image above) that suggested a 2.5-3.0nm total dielectric thickness (which must include at least one monolayer each for upper and lower barriers) for the gate insulator, instead of the 1.2nm (~six atomic layers) silicon oxide layer grown in Intel’s 65nm chips.
The company also has introduced a new (secret) combination of metal materials for the transistor gate electrodes, though still requiring one for NMOS and another for PMOS. In addition, the 45nm interconnects also utilize copper wires with a low-k dielectric to help improve performance and reduce power consumption.
Bohr noted that the 45nm Penryn has about 410 million transistors in the dual-core version (twice that for quad-core). Most of the 45nm transistor budget increase is in increased cache, with additional computing capabilities including 50 new streaming SIM extensions and SSE4 instructions (a mix of integer and floating-point instructions).
The shift to 45nm processes isn’t as daunting from a manufacturing standpoint, Bohr noted — the process still utilizes “cost-effective” 193nm dry lithography techniques, and most of Intel’s production equipment can be reused for the 45nm HK+MG processes, he explained. The few added process steps amount to only “a small single-digit percentage increase” in manufacturing costs, “a small price to pay when doubling transistor density,” he said.
Intel is now running the 45nm Penryn chip on five products — a notebook with dual-core processor, dual- and quad-core desktops, and dual- and quad-core server systems — with at least another 10 systems in design on 45nm, said Steve Smith, VP of Intel’s DEG Group Operations. He added that the very first 45nm wafers that came out of the fab, assembled and packaged, were able to boot OS and run code “within two or three hours.” He noted that all of the five systems shown are expected to start shipping in 2H07, though the exact sequence and mix depends on OEM readiness. The first 45nm devices will come out of Intel’s D1D fab in Oregon in 2H07, followed “a few weeks” later by Fab 32 in Arizona. Intel’s under-construction Fab28 in Israel will be ramping the 45nm process by 1H08.