ISS 2007 REPORT: Riding the DFM revolution

By Phil LoPiccolo, Editor-in-Chief

As the industry crosses the 100nm barrier, design-for-manufacturing (DFM) tools will be the key to helping chipmakers deal with a new class of systematic defects and improve yields, according to Dan Hutcheson, CEO of VLSI Research, speaking at the Industry Strategy Symposium (ISS) conference last week in Half Moon Bay, CA. And in the process, he said, DFM “will revolutionize the nature of competitive advantage in the semiconductor industry.”

To illustrate the dynamic, Hutcheson showed the distribution of three types of defects — systemic defects (i.e., from design flaws), manageable random defect (from particles), and unmanageable defects (from unknown causes) — as yield increases for typical chipmakers building 90nm devices (see figure above). Prior to 100nm processes, systematic defects accounted for a much smaller percentage of defects, he explained, because with larger feature sizes design problems were relatively easy to identify and correct.

Now, however, systematic defects dominate the picture early on in the production ramp. The increase stems from a new class of defects that Hutcheson calls “pseudo-random” defects, which may appear to be random because sometimes the die is good and sometimes it’s not — but they’re not random, he says, because they always show up in the same spot.

These defects result from normal process variations at the nanochip scale, and “this is what’s killing everybody,” according to Hutcheson. “What’s happening is that the process bandwidth is getting so narrow that you either widen process bandwidth and lose device performance, or go for device performance and lose bandwidth and end up with these process marginalities that are right on the edge.” Even though the defects look random, you can fix them with design tools, he says, and this is driving interest in DFM.

In fact, adopting DFM to address this new class of pseudo-random systematic defects can confer an enormous competitive advantage. To demonstrate the point, VLSI Research compared percent yield vs. time to yield for two fabs ramping to a new technology node, with one fab using what VLSI termed “world-class” DFM and the other using “worst-in-class” DFM. After modeling the data based on real defect densities from different chipmakers (and normalizing in terms of wafer sizes, die sizes, etc.), VLSI found that after one year the world-class DFM fab had achieved 80% yield, vs. just 10% yield at the worst-in-class DFM fab.

Converting this to an annualized revenue basis showed huge differences. In the first year, the company with world-class DFM brought in more than $3 billion, and another $4 billion in year two — while the company with worst-in-class DFM brought in just over $400 million in the first year and $1.5 billion in the second year (see chart below). Over the five-year period in which equipment is depreciated, the world-class DFM fab would bring in $15 billion, or a sustainable 20% capital expenditure rate. In contrast, the worst-in-class DFM fab would bring in $8.5 billion, which means its capital spending rate would be a nonsustainable 35%, Hutcheson explained.

Moreover, the revenue difference between the two companies over five years would pay for two $3-billion 300mm fabs with $500 million to spare. “Both companies spend the same amount of money for the fab,” he said, adding: “So who’s going to be in business in five years?”

The bottom line, Hutcheson contended, is that a chipmaker will not be competitive in the nanochip era without overcoming fundamental DFM issues. “There’s a relinking of design and manufacturing going on that we haven’t seen since the evolution of EDA tools,” he said, “and it’s causing a fundamental shift in the industry.” — P.L.


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