Mears Technologies addresses gate leakage with band engineering process

by Debra Vogler, Senior Editor

A key problem looming for semiconductor manufacturing at the 45nm node and beyond is gate leakage, yet there’s no high-k/metal gate solution ready to tackle it in a manufacturing environment. However, Mears Technologies recently announced what it believes to be a solution — using band engineering to re-engineer the physical properties of silicon.

The company’s band engineering techniques were developed using quantum mechanics simulations without using external assumptions, according to Robert Mears, company founder, president, and CTO, who described the solution called MST Platform to WaferNEWS. “We know the sorts of fields the channel will experience at the 32nm node.” The technology is an epitaxial silicon stack inserted into a standard CMOS flow, which Mears says involves no new materials and uses standard industry tooling. In addition to providing gate leakage reduction for bulk CMOS, the company says it also provides such benefits to process-induced strain and SOI applications.

Proprietary recipes were developed by the company to deposit very thin (approximately 100Å thick) layers of epitaxial silicon. This epi stack is a channel replacement layer, and the result is that the silicon layer appears to behave more like a laminate — particularly with respect to its electronic properties, explained VP of engineering Scott Kreps. “Although it’s still single crystal silicon, it’s stratified so that there are layers in which electrons find it easier to travel in the plane of the device, but not very easily in the vertical direction,” he said (see figure).

The epi stack material’s inherent anisotropy is the origin of its two advantages, according to Kreps. In the plane, it is a bit easier for carriers, both electrons and holes, to travel (see figure). “But most importantly, in the vertical direction, it is much harder for electrons and holes to travel,” said Kreps.

The company reports it has achieved gate leakage reduction of up to 70% in NMOS transistors and up to a 90% reduction in gate leakage for pMOS transistors, while maintaining drive current. Kreps said that the company has proven its technology at the 130nm node and demonstrated it at the 90nm node, having built “dozens of fully integrated device runs,” and “produced over 1000 wafers of epitaxial deposited films.” He added that although the first couple of customer implementations are likely to be at the 45nm high-performance node, where gate leakage is the overriding issue, the company sees no barriers to scaling the technology even beyond the 22nm node. Mears’ solution is also backwards applicable to 65nm, he noted.

Many IDMs and foundries may have already selected their tools and are nearing completion of their process development at the 45nm node, but Kreps insists that there is still quite a bit of flux in terms of what people will do for the high-performance node. “The low-power node generally comes out first and is fairly well set for many companies,” he said. “But the companies we are in discussion with have indicated that clearly, there are some unresolved issues for the 45nm high-performance node.” — D.V.


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