by Jeff Demmin, Contributing Editor, WaferNews
An update to the International Technology Roadmap for Semiconductors was released in December, and though modifications were minor before next year’s full ITRS revision, as always the changes from the previous annual edition provide key indicators of trends in the industry. An examination of the new content in the assembly and packaging chapter, for example, illuminates concerns about package substrates keeping up with advances in silicon technology, as well as a variety of challenges in thinned-die packaging.
The first sentence of the A&P chapter describes a challenging landscape, in which “the pace of change in assembly and packaging has accelerated as packaging is increasingly a limiting factor for both product cost and performance.” Nearly every category of the “Near-Term Difficult Challenges” table has been updated, with the most noticeable changes in the issues associated with substrates and thin packaging.
For substrates, one item added to the list is a need for solutions to meet the I/O density of the latest area-array silicon devices. A related item added to the list of “Long-Term Difficult Challenges” predicts a “brick wall” at 5-micron lines and spaces, suggesting the current trajectory for substrate technology will fall short of high-density and high-performance requirements.
Part of the answer to substrate challenges lies in achieving better control of the material properties, and several new lines were added to the table showing the requirements for substrates. The coefficient of thermal expansion is highlighted, with no known solutions seen for controlling the z-direction thermal expansion for the common rigid and build-up substrate structures. Novel structures and materials will likely be needed there.
One approach to solving substrate challenges suggested by the ITRS is to incorporate “silicon-like” production and process technologies. This guidance could lead some researchers to take a close look at previous-generation wafer fab equipment for substrate manufacturing concepts, and perhaps stimulate a “hand-me-down” situation whereby aging wafer fabs get pressed into service for substrate production.
Several new “Difficult Challenges” have been added to the thinned-die packaging section of the Roadmap. One such challenge relates to the substrate area, where the impact of different carrier materials is seen as a new concern. Different kinds of materials (organics, silicon, ceramics, glass, and laminate core) are being pressed into service for different applications, and the complications to the process flow need to be addressed. Another item, “Establish infrastructure for new value chain,” also relates to implementation and integration matters, indicating that this area is moving beyond the basic engineering tasks into the logistical and business issues resulting from proliferation of the technology into high-volume applications.
The itemized list of “Difficult Challenges” contains 10 new issues, with only two deleted from last year’s list: singulation technology for low-k wafers, and design tools for in-package decoupling. Low-k processing and design tools have certainly been highlighted in recent editions of the ITRS, so perhaps the Roadmapis serving its purpose. — J.D.