SEMATECH, IBM: We’re using high-k, too

January 29, 2007 – Hours after Intel uncrated its 45nm transistors using high-k dielectric and metal gates for shipment later this year, SEMATECH and the IBM Common Platform Alliance both released statements indicating that they, too, are in the final stages of tinkering with the technologies. Both camps said they would be discussing details at upcoming venues.

IBM says that its work with partners AMD, Sony, and Toshiba also has led to insertion of high-k metal gates into a manufacturing line at its East Fishkill, NY facilities, and will be incorporated into 45nm chips starting sometime in 2008. Like Intel, IBM indicated that adding the high-k process to its manufacturing lines did not require major tooling or process changes.

Mukesh Khare, senior manager of IBM Research, provided WaferNEWS with few extra details about their process, saying only that they’re using “conventional processing” and that they weren’t “cutting any corners,” and that further details will be presented at an unidentified industry event sometime around midyear. Although high-k could be used “anywhere we like,” he did acknowledge that the first application would be for high-performance, with an eye toward IBM’s internal Power work.

He also pointed out that only the specific Common Platform alliance partners mentioned in the PR are involved in this high-k work: IBM, AMD, Sony, and Toshiba (note no Samsung or Chartered). Volume production ramp is scheduled vaguely for sometime in 2008, but Khare noted that work is focused in Fishkill and so IBM will be first to ramp production — then it’s up to those specific partners to decide when and how to take the technology back to their own facilities for production.

Meanwhile, SEMATECH says it has successfully integrated pMOS and nMOS materials into highly-scaled CMOS devices with low threshold voltage “similar to conventional polysilicon/SiO2 devices,” and with ultrathin equivalent oxide thicknesses “in the range of 1.0-1.2nm.” The group says the CMOS devices were fabricated with conventional gate-first, high-temperature processing flows, without using substrate counter-doping or other extraordinary or complicated measures, and showed no reduction to drive currents or other performance metrics.

Earlier this month, NEC Electronics revealed its CB-55L cell-based IC using its 55nm “UX7LS” process technology, which it says is the first 55nm device to use high-k dielectric to reduce leakage current. The device, initially available only to makers of digital cameras and other portable devices, also incorporates DM techniques including on-line/on-the-grid layout to prevent excessive parameter variations, resulting in “very high reliability,” the company claims.


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