SEMATECH, TEL partner for 3D interconnects

January 25, 2007 – SEMATECH and Tokyo Electron Limited (TEL) have entered into a multiyear joint development program to improve prospects for using 3D interconnect technology and high-mobility channel materials in advanced semiconductor manufacturing, both sides said today in a statement.

The planned collaboration will focus on two separate projects. A three-year program will focus on transcending barriers to 3D processing in volume manufacturing, including cost-of-ownership modeling, process benchmarking, establishing standards, technology roadmapping, and the formation of through-wafer silicon vias. This work, which will support development of low-k materials for 45nm-32nm node processes, will utilize TEL’s Si etch experience for high-aspect ratio, high-rate etch development capability at its R&D labs in Japan.

TEL also will upgrade an existing low-k dielectric etch tool in SEMATECH’s R&D fab subsidiary, Advanced Technology Development Facility (ATDF), improving the process uniformity and capability of the chamber and providing more flexibility in understanding the etching of porous low-k materials, the firms said.

The other project, a two-year venture combining SEMATECH’s frontend processes and TEL engineers, aims to advance development of alternative epitaxial materials (namely silicon germanium) and integration with such materials with high-k metal gates on advanced short channel devices.

“3D technology offers the prospects of improved performance and functionality, reduced power and chip area, reduced development costs, and faster time to market over conventional, two-dimensional designs,” said Sitaram Arkalgud, SEMATECH’s Interconnect director, in a statement. He adding that “all sections of the industry must come together to address the availability of the proper infrastructure” and realize 3D’s promise to allow chipmakers to heterogeneously integrate incompatible fabrication technologies into a single stacked system.


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