February 16, 2007 – The Fabless Semiconductor Association (FSA) has released the first tool in a planned “ecosystem” of IP deliverables that aims to address pain points of IP integration by enabling more effective communication between IP vendors, fabless companies, IDMs, and foundries.
The Hard IP Quality Risk Assessment Tool v1.2, first in FSA’s “IP ecosystem” tool suite, collects information about an IP vendor, including design methodology and IP under evaluation, to enable risk assessment across seven criteria: IP design, integration, verification, process technology, product documentation, reliability, and test.
Developed by the FSA’s Hard IP Working Group with participation from foundries including Chartered, IBM, Samsung, SMIC, TSMC and UMC, the tool is aimed for use as third-party IP evaluation and comparison for integrators, evaluation of IP quality within IP repositories such as foundry IP programs, and internal IP reuse evaluation for fabless companies or vendors that create their own IP, the FSA stated.
“Streamlined and effective metrics at IP hand-off is an intelligent and cost-effective way to understand and minimize ‘hidden’ costs,” said Raminderpal Singh, chair of the Hard IP Working Group, from IBM’s systems and technology group, in a statement. “This effort has brought together vendors and integrators from across the industry to create an ‘apples-to-apples’ comparison of hard IP cores.”
“This tool presents a baseline for discussion between IP vendors and IP integrators that enables focus to be drawn quickly to resolving any areas of concern. This is a win/win for the industry,” added Norbert Diesing, director of technology forecasting at PMC-Sierra.
Development work on a second tool in the “ecosystem,” focusing on intangible aspects of third-party IP licensing, is expected to be released in 3Q07, followed by two more tools addressing IP technology and manufacturability slated for release in 2008.