February 14, 2007 – IBM says it expects a new e-DRAM on-chip memory technology with 10x faster access times will be ready for its 45nm process Roadmap, to be included in chips produced next year.

The eDRAM technology, designed in stress-enabled 65nm SOI using deep trench, contains over 12 million bits and high-performance logic, and essentially triples the memory in the same footprint with one-fifth the standby power of conventional SRAM, the company said in a statement. Details are being presented at this week’s International Solid State Circuits Conference (ISSCC).

The chip’s 1.5ns latency is about 10x the speed of 10-12ns for conventional DRAMS, and almost as fast as the 0.8-1.0ns for SRAMs, noted the Wall Street Journal and MarketWatch.

“As we look into the processor roadmap, this is one of the most difficult things to solve. We were basically memory-limited in the high-power processors, so this has been very significant for us,” said Lisa Su, VP for semiconductor research and development at IBM, quoted by the Associated Press.

Specs of IBM’s eDRAM technology

Cell size: 0.126 mm2
Power supply: 1 V
Availability: 98.7%
Tile: 1K RowX16 Col X146 (2Mb)
AC power: 76 mW
Standby keep alive power: 42 mW
Random cycle time: 2ns
Latency: 1.5ns

Source: IBM