February 13, 2007 – Renesas Technology Corp. and Matsushita Electric Industrial Co. Ltd. say they have developed a technique that achieves stable operation with 45nm bulk CMOS, instead of silicon-on-insulator (SOI), for SRAM that can be embedded in system-on-a-chip (SoC) devices and microprocessors.
In a paper at this week’s International Solid State Circuits Conference (ISSCC), the companies say they built a 45nm 512Kbit test chip incorporating two different memory cell designs (cell areas of 0.327 sq. micron and 0.245sq. micron), the smaller of which done with a reduced processing dimension margin.
Managing threshold voltage variation (both global and localized) caused by transistor miniaturization has been problematic for SRAM designers for several nodes. Now, the answer that the teams have come up with is six-transistor type SRAM memory with two elements. One, a read-assist circuit, performs automatic adjustment linked to Vth variations, employing resistance of passive elements in a compensation function (laid out like a memory cell) that adjusts voltage automatically with respect to temperature and process variations.
The other element, a write-assist circuit, uses eight power supply lines in such a way that the isolation needed for the write operation is performed only where necessary. The hierarchically structured power supply wiring reduces power supply line capacitance in critical areas, allowing the power supply line potential to be dropped to a low potential at high speed, the companies explained.
As a result, even under worst-case conditions (-40C, minimum operating voltage, and worst-case process conditions), the new write-assist circuit provides a major improvement in SRAM write speed compared to an SRAM design in which it isn’t used, the companies claim.