Laser annealing is on the front burner at Ultratech

by Debra Vogler, Senior Technical Editor

Moving beyond its pilot production efforts with logic manufacturers worldwide, Ultratech Inc. highlighted application of laser spike annealing (LSA) to DRAMs in a joint paper with Samsung at the recent IEDM conference 1.

Yun Wang, Ultratech’s VP and chief technologist for laser processing, summarized key findings for WaferNews. Using LSA for a DRAM with a tungsten gate stack minimizes pattern effects when inserted into the contact process flow (i.e., BEOL), but Wang indicated the company is making efforts to demonstrate that LSA can be inserted at any point in the process — not just at the contact process — and still minimize pattern effects.

The researchers found 4% and 14% improvements in drive currents for peripheral nFET/pFET transistors, respectively, and also noted an improvement in cell transistor drive current and leakage with no reliability degradation or extra defects. The team attributed the reduction in leakage current to defect-curing by the high-temperature annealing (1350°C) and reduced depletion width by increased activation. 1

Wang maintains that the Samsung paper describes the first application of LSA to DRAMs, while all other papers are for advanced logic devices. “DRAM uses tungsten gates, which pose more complications — the cell where data is stored requires low leakage for longer data retention and lower power consumption,” he explained.

Ever since unveiling the first application of laser annealing technology in June 2003, Ultratech has been working to ready the technology for more advanced nodes. With the need for thinner gates as the industry approaches 32nm half-pitch, annealing times will have to be even faster, posing problems for flash lamp-based rapid thermal annealing and even laser diode bar technologies, explained Art Zafiropoulo, chairman/CEO/president, in an interview with WaferNews. He predicts that competing technologies will not be extendible to 32nm and will also have cost-of-ownership limitations.

“DRAM is still lagging in junction formation by about one generation,” said Zafiropoulo. “That’s why we targeted logic first and in early 2006, we started work on memory.” The company is currently pursuing integration of its technology into logic devices at various sites worldwide.

There’s also an interesting side note to the technology story. In 2000, at the behest of a major customer that wanted a second (and larger-supplier) source for the company’s laser annealing technology, Ultratech licensed much of its melt technology to Applied Materials Inc., which had selected the laser diode for further development. According to Zafiropoulo, Ultratech did not want to pursue melt technology for advanced nodes due to its inherent limitation: so-called stitching effects (i.e., pattern effects) that arise when square waves are used for scanning.

(Ironically, the investor community has also pinpointed the company’s size as an issue that may be hurting growth. Earlier this month, a New York-based hedge fund claiming to be Ultratech’s largest shareholder publicly called for a sale of the company to a larger organization in order to better monetize growth prospects.)

Asked to comment on whether or not Applied Materials will license Ultratech’s current sub-melt laser technology, Zafiropoulo claimed not to know the answer, implying that there are legal issues up for debate. He did note, however, that Applied has acknowledged using the new technology for sub-melt laser annealing. — D.V.

1 G. Buh, G-H. Yon, T. Park, J-W. Lee, J. Kim, Y. Wang, et. al., “Integration of Sub-melt Laser Annealing on Metal Gate CMOS Devices for Sub-50nm Node DRAM,” IEDM Technical Digest, p. 33.4.1-33.4.4, (2006).


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