New lithography strategy could double contamination challenge

By Hank Hogan

When it comes to next-generation lithography, the semiconductor industry may be doing a double take-and that could mean double duty for contamination control. There’s concern within the industry about a lithography shortfall when the 32-nanometer half-pitch node enters production in about five years. Doubts have arisen that the leading contender, extreme ultraviolet lithography (EUVL), will be ready in time.

To counter this, technologists are considering double patterning, in which only part of the pattern is imaged and etched on the first pass. A second pass takes care of the rest. By splitting up the lithography process, the achievable minimum pitch is decreased without having to use a shorter imaging wavelength or make other changes (see Figure).

“You’re basically using what’s available today-no new materials. Everything is more or less standard,” says Kurt Ronse, director of the lithography department at the nanotechnology and nanoelectronics research center, IMEC (Leuven, Belgium).

Although double patterning does require a stringent overlay tolerance between the two halves, Ronse notes that achieving this doesn’t require new fundamental research and development. Also, because future lithography processes will need to attain tight overlays anyway, hitting the specification required for double patterning will be required no matter what lithography technique is used.

The downside of double patterning is twofold. First, the most critical layers must go through lithography and etch twice, which cuts throughput. Second, there could be a yield hit. Two passes, plus extra handling, means doubling the chance of picking up a particulate, contaminant or other killer defect. Hence, double patterning will demand an even greater emphasis on contamination control in the most sensitive parts of the manufacturing process.

As a result, double patterning could be both the easiest way to achieve 32 nm manufacturing and the most expensive, at least for volume production. Thus, it may only be practical for the initial ramp up, which could start in two to three years.

As for EUVL, Michael Lercel, director of lithography for the research consortium SEMATECH (Austin, TX), says there has in fact been progress. In November, SEMATECH engineers reported shipping and handling lithography masks without adding defects. They also reported developing an integrated smoothing and deposition process to make more perfect mask blanks, a fundamental requirement that Lercel says isn’t easy to achieve. “You need completely defect-free mask blanks, and this involves a tremendous number of depositions of multilayer reflector material.”

For his part, Lercel believes that EUVL is on track but notes that double patterning is also attracting attention. A May 2006 SEMATECH survey listed the technique as a second choice for 32 nm manufacturing, with EUVL being the first. In the previous survey, done in 2004, the two-step process didn’t even make the list, in part because it was thought EUVL would be ready in time.

Double patterning is seen as a likely strategy in future semiconductor manufacturing because it allows the use of well-known optical lithography instead of new extreme ultraviolet lithography (EUVL). It requires taking a circuit pattern (on left), splitting it into two masks (middle) and then using both in succession to pattern a single layer in the final chip circuit. Image courtesy Kurt Ronse, IMEC.
Click here to enlarge image

With the deployment date approaching, and concerns growing, however, the two-step strategy is suddenly now being seriously considered. The final determinant may not be a technical issue. “The industry is now evaluating how feasible the economics are of introducing 193-nanometer double exposure,” says Lercel.


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