SEMATECH: Planar CMOS, not finFETs, favored through 22nm

February 6, 2007 – SEMATECH’s engineers will focus on planar CMOS approaches and new channel materials for transistors at the 22nm half-pitch node, relegating FinFET device structures as an alternative approach, the consortium said in a statement. The position follows input from member organizations and experts at a recent IEDM panel.

“It appears there is still enough life left in planar scaling for the nearer term, especially with the incorporation of Ge in to Si devices,” said Raj Jammy, director of SEMATECH’s Front End Processes (FEP) division, in a statement. He acknowledged, though, that 3D devices and associated design capabilities will be needed to realize FinFET technology “in the near future.”

Many detailed presentations at IEDM discussed finFETs as well as on fin structures for RAM cells, with results displayed by SEMATECH as well as IMEC, Samsung, and Toshiba. Most chipmakers agree that FinFETs won’t be used before the 32nm node, even though that at least for state-of-the-art low-standby power digital circuits, finFETs provide equivalent performance to planar transistors with 1/10th the leakage current and 50% less battery power consumption, and no extra manufacturing costs.

Engineers have used various tricks to induce strain at the channel to improve mobility, but “new channel materials are the direction we want to go,” including SiGe, Ge, and more untested III-V elements, stated Hsing-Huang Tseng, chief technologist of FEP and program manager. Several approaches SEMATECH is investigating involve Si/SiGE for nMOS and Ge/SiGe for pMOS channels, or III-V materials on Si platform for nMOS in the near future, applied as ultrathin epitaxial layers grown selectively on Si to minimize defectivity.

Tseng noted that serious challenges remain for extending the life of planar CMOS, such as reducing defects in Ge or Si-Ge layers, preserving mobility advantages for bulk materials when epitaxial channels are grown on Si; and controlling Ge band-to-band tunneling, which increases overall leakage current.

Beyond the 22nm node, in addition to planar device efforts using new channel materials, SEMATECH will also probe usability of FinFETs that promise better short-channel control and greater speed. However, there are still too many unsolved manufacturing and design challenges involved with implementing these 3D transistors to feasibly consider it before the 22nm node, the consortium claims.

“Scaling CMOS technologies with new channel materials appears to have greater potential in the nearer term, but we will continue to pursue non-planar approaches for more distant technology generations,” said Jammy.


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