Modeling becomes key to advanced lithography

by M. David Levenson, senior technical editor

The prominence of a dedicated joint session and a panel discussion on “computational lithography” at this year’s SPIE Advanced Lithography Symposium (Feb. 25-March 2, San Jose, CA) — not to mention the recent quarter-billion-dollar purchase of Brion by ASML — illustrate the growing importance of resolution enhancement tricks that have made it possible to approach the 45nm node using an exposure wavelength four times larger. Making sure that those tricks actually work before fabricating complex masks has become crucial. Ambitious players are emerging in this new field, with varying amounts of traction, insight, and chutzpah.

Invarium Inc., founded in 2003, has been working to refine the many modules of its forward simulation model of the lithography process, and now claims better accuracy than anyone in predicting final resist patterns. To improve model accuracy further, they have attracted industry guru Chris Mack, one of the pioneers of predictive simulation. “I always thought my algorithms would work better than what they use for OPC,” Mack told WaferNEWSin a phone interview. “Now we will find out if I am right.”

The current accuracy of the Invarium models through the process window seems quite impressive, but modeling is only as good as the characterization of the process. Much of Invarium’s core IP is in the parameterization area. CEO Roy Prasad reported having two paying customers for Invarium’s OPC outsource services, and a plan to provide and support software to be run in house by future large customers.

However, the challenge is about to get much harder, as pointed out by Invarium CTO Apo Sezginer and Wolf Staud, director of marketing. The problem is double patterning, where the CD process window lives in a 9+ dimensional space and the overlay specs have to be many times better than current hardware technology. “Even with unreasonably optimistic assumptions, a +/-10% (full range) CD uniformity is not reasonable for [double-patterning] spaces at 40nm half-pitch,” remarked Sezginer. Statistical analysis is less depressing, though. With 3nm of overlay and 60nm of defocus, it is possible to have a 4.5nm 3[sigma] for spaces, if errors add in quadrature. Getting the etch uniformity tight enough will require model-based proximity correction for the etch process, according to Sezginer.

Other difficulties include BARC behavior in double patterning, which must not obscure alignment marks but also must prevent reflections from the first pattern when the second is printed. That issue is being addressed by Invarium in collaboration with IMEC, according to Staud. Also, “stubs” that connect circuits printed on different exposures can affect the linewidths of features printed in the same exposure, even though those features are one full pitch unit away in the circuit. Gates and other critical circuit elements have to avoid these “stub” regions, according to Sezginer (see slides above and below). Some patterns with triangular symmetry cannot be divided in half successfully.

Meanwhile, Luminescent Technologies, a venture capital-backed company started in 2002, is touting the full-chip results its customers have been getting for 45nm and 32nm contact layer patterns (140nm pitch and 110nm-100nm pitch, respectively) using the company’s “inverse lithography technology” (ILT). This system samples the desired image on a grid (as does Brion) and then “inverts” the pattern mathematically using the patented “level-set” method of Luminescent founder Stan Osher to produce an ideal “gray-scale” mask pattern. It then creates an approximation to the ideal case that can be fabricated in current mask technology.

The result is claimed to be the fabricatable mask pattern that best projects the desired image. Serifs, assist features (if needed), and the printing features are all optimized simultaneously by the “Luminizer” system, without the need for script-writing, according to company CEO David Fried, in an interview with WaferNEWS. Side-lobe printing even at the edge of process windows is automatically avoided. The net result is a larger DOF than can be obtained by other OPC systems, he said.

Computation is done on hardware supplied by Luminescent that “soon” will include dedicated accelerator cards using FPGA technology (like Brion’s), according to Director of Engineering Bob Gleason — but even without acceleration, the ILT system runs as fast at 65nm as conventional “edge-placement” OPC, he reported. The scaling laws are such that it will run faster at 45nm, he claims. For 45nm contact and poly layers, mask writing takes <8 hours for a full chip, less than reported for conventional OPC by Luminescent's customers. The mask worked better, too, with 100nm more depth of focus, according to Leo Pang, VP of marketing. -- M.D.L.


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