REPORT FROM SPIE: Double double, toil and trouble!

by M. David Levenson, Editor-in-Chief, Microlithography World

Double-patterning technology (DPT) emerged as the most viable next patterning method at last week’s SPIE Advanced Lithography Symposium. Progress in water immersion exposure technology since the last meeting has been so convincing that its insertion into manufacturing at the 55nm and 45nm generations (as reported by Toshiba, STMicro, and others) is not likely to be interrupted. However, the refractive index of water sets a resolution limit, and the consensus is that the new fluids and systems that would push beyond that limit cannot be ready in time. Thus, some evolutionary step has to be taken to extend immersion technology and keep up with Moore’s law. Double patterning seems to be the step that will take us to 32nm.

There are at least four distinct near-term options for double-patterning lithography, which is distinct from “double exposure.” In double exposure (widely used with alternating phase-shifting masks), two images from two distinct masks are printed into the same resist layer, which is subsequently developed and etched into the substrate. The laws of optics forbid such methods from decreasing the pitch of patterns exposed in conventional resist, although undesirable features of the image can be cut out. While proposals have been made for unconventional resist materials that might overcome the “single-photon response” limit, none has yet appeared. Thus, higher resolution through double-patterning technology requires sequential exposure and development of different resist films and multiple etch steps to transfer the resist patterns into the substrate.

Two of the four double-patterning options interdigitate and stitch together optical exposures to form a final circuit. They differ in the tone of the process, with the most common option employing positive resist, thus making the line CDs independent of overlay, and the other making the space CDs independent of overlay, generally by employing negative resist. (Maaike Op de Beeck of IMEC showed an elegant negative-tone DPT process that used positive resist and RELACS post-processing to print 50nm 1:1 trenches for metal layers.) Both methods employ large pitch patterns with low duty factors, and overlay images to place a narrow feature of the later exposure in the center of the wide feature of an earlier one.

Since overlay error becomes CD nonuiformity in this kind of DPT, overlay precision and metrology are key enablers. Bill Arnold, chief scientist of ASML reviewed the status and challenges in his keynote address to the Metrology, Inspection and Process Control Conference. He reported that IMEC had achieved 32nm line-space patterning with the positive-tone process, using a 0.85NA exposure tool — with a k1 factor of 0.14, well below the 0.25 single-exposure limit. Jan Mulkins and Jos de Klerk, both of ASML, separately reported experiments that achieved 3nm overlay precision on a single-wafer stage of the Twinscan system, just barely enough to proceed toward 10% CDU at 32nm.

The other two double-patterning options avoid the worst overlay problems through self alignment, but require more complex processing. In these “spacer” processes, the first optical-exposure pattern is etched into a sacrificial layer. Another material is then deposited conformally on the sides of this spacer to a thickness that defines the final pattern. In positive tone spacer processes, the first sacrificial layer is removed and the pattern formed by the deposited material is etched into the final hardmask or substrate. At an invitation-only Applied Materials seminar, Xumou Xu presented a method of this type that achieves 32nm resolution using an Applied APF amorphous carbon spacer and hardmask (see image below).

In the negative-tone spacer process, reported by Woo-Yung Jung of Hynix Semiconductor, a second hardmask material is deposited over the first added layer and then partly removed. Selective etching then takes away the first added (spacer) material (a plasma-deposited carbon polymer in Jung’s case), leaving two hardmask features — one patterned by resist and one by deposition between spacers — with half the original pitch. Jung claimed that his process was the least sensitive to errors and suitable for patterning NAND flash memory at 35nm with 0.93NA ArF exposure. In most cases, a final trim exposure would be needed to remove unwanted connections and create the final circuit.

If this all sounds difficult to do, it is. Other challenges include fracturing circuit designs into mask patterns that can be fabricated in two or three exposures, rather than four or five. That will require restricted design rules, according to Hans Stork of TI. Maskmaking procedures will have to be improved, so that related masks are made sequentially on the same machine and with the best relative overlay accuracy, according to Peter Buck of Toppan. The CDs of features created in different ways will comprise different populations that will have to be distinguished in test and metrology, and the processes will need to be tweaked accordingly. As trouble-prone as double-patterning technology sounds, it does appear inevitable for the near future unless EUV or some other new technology emerges in time. — M.D.L.


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