TSMC, Nvidia tip 65nm embedded DRAM

March 6, 2007 – TSMC and customer Nvidia say they have produced functional 65nm embedded DRAM verified “first time right,” targeting the technology at digital consumer/gaming devices, multimedia processors, and high-end networking.

The new 65nm eDRAM process, built on 10 metal layers using copper low-k interconnect and NiSi transistor interconnects, has nearly 50% smaller cell and macro sizes than previous high-density memory generations, and less than a quarter the cell size of its SRAM counterpart. Macro densities range from 4Mbit-256Mbit.

The process is being used first for Nvidia’s new handheld GPU. “The efficiencies of the embedded DRAM process allowed us to raise the bar for features found in mainstream cell phones,” said Michael Rayfield, GM of the company’s handheld division.

TSMC ramped to 65nm production in 2Q06 and started 90nm embedded DRAM production in 1Q06.


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